PSD833F2 datasheet(56/110 Pages) STMICROELECTRONICS

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PSD835G2

PSD8XX Family

The

PSD835G2

Functional

Blocks

(cont.)

Control

Direction

Defined In

JTAG

Mode

PSDsoft

Setting

Enable

Declare

1 = output,

MCU I/O

pins only

(Note 3)

0 = input

(Note 1)

Declare pins

PLD I/O

and logic

(Note 1)

equations

Data Port

Selected for

(Port F)

MCU with

non-mux bus

Address Out

Declare

1 (Note 1)

(Port E, F, G)

pins only

Declare pins or

Address In

logic equation

(Port A,B,C,D,F) for input

Micro

⇔Cells

Peripheral I/O

Logic equations

PIO bit = 1

(Port F)

(PSEL0 & 1)

JTAG ISP

Declare pins

JTAG_Enable

(Note 2)

only

Table 17. Port Operating Mode Settings

*NA = Not Applicable

NOTE: 1. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the

individual output enable product term (.oe) from the CPLD AND array.

2. Any of these three methods will enable JTAG pins on Port E.

3. Control Register setting is not applicable to Ports A, B and C.

9.4.2.1 MCU I/O Mode

In the MCU I/O Mode, the microcontroller uses the PSD835G2 ports to expand its own

I/O ports. By setting up the CSIOP space, the ports on the PSD4000 are mapped into the

microcontroller address space. The addresses of the ports are listed in Table 6.

A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the

Control Register (Port E, F and G). The MCU I/O direction may be changed by writing to

the corresponding bit in the Direction Register, or by the output enable product term. See

the subsection on the Direction Register in the “Port Registers” section. When the pin is

configured as an output, the content of the Data Out Register drives the pin. When config-

ured as an input, the microcontroller can read the port input through the Data In buffer.

See Figure 22.

Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default.

They can be used for PLD I/O if they are specified in PSDsoft.

9.4.2.2 PLD I/O Mode

The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro

⇔Cells, and/or as an

output from the CPLD’s Output Micro

⇔Cells. The output can be tri-stated with a control

signal. This output enable control signal can be defined by a product term from the PLD, or

by setting the corresponding bit in the Direction Register to ‘0’. The corresponding bit in the

Direction Register must not be set to ‘1’ if the pin is defined as a PLD input pin in PSDsoft.

The PLD I/O Mode is specified in PSDsoft by declaring the port pins, and then specifying

an equation in PSDsoft.

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