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PSD833F2 датащи(PDF) 64 Page - STMicroelectronics

номер детали PSD833F2
подробное описание детали  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD833F2 датащи(HTML) 64 Page - STMicroelectronics

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PSD835G2
PSD8XX Family
63
The
PSD4000
Functional
Blocks
(cont.)
DATA OUT
REG.
DQ
D
G
Q
DQ
DQ
WR
WR
WR
ADDRESS
EXT. CS (PORT F)
ENABLE PRODUCT TERM (.OE)
ALE
READ MUX
P
D
B
CONTROL REG.
DIR REG.
ENABLE OUT
CPLD INPUT (PORT F)
ISP OR BATTERY BACK-UP (PORT E)
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
ADDRESS
A[ 7:0] OR A[15:8]
CONFIGURATION
BIT
Figure 28. Ports E, F and G Structure
9.4.8 Port F – Functionality and Structure
Port F can be configured to perform one or more of the following functions:
t MCU I/O Mode
t CPLD Output – external chip select ECS[7:0] can be connected to Port F (or Port C).
t CPLD Input – as direct input ot the CPLD array.
t Address In – additional high address inputs. Direct input to the CPLD array, no Input
Micro
⇔Cells latching is available.
t Latched Address Out – Provide latched address out per Table 29.
t Slew Rate – pins can be set up for fast slew rate.
t Data Port – connected to D[7:0] when Port F is configured as Data Port for a
non-multiplexed bus.
t Peripheral I/O Mode
9.4.9 Port G – Functionality and Structure
Port G can be configured to perform one or more of the following functions:
t MCU I/O Mode
t Latched Address Out – provide latched address out per Table 29.
t Open Drain – pins can be configured in Open Drain Mode



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