PSD833F2 datasheet(11/110 Pages) STMICROELECTRONICS

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PSD8XX Family

PSD835G2

Pin*

(TQFP

Pin Name Pkg.)

Type

Description

PE3

I/O

Port E, PE3. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. Latched address output.

3. TDO output for JTAG/ISP interface.

PE4

I/O

Port E, PE4. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. Latched address output.

3. TSTAT output for the ISP interface.

4. Rdy/Bsy — for in-circuit Parallel Programming.

PE5

I/O

Port E, PE5. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. Latched address output.

3. TERR active low output for ISP interface.

PE6

I/O

Port E, PE6. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. Latched address output.

3. Vstby — SRAM standby voltage input for battery

backup SRAM

PE7

I/O

Port E, PE7. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. Latched address output.

3. Vbaton — battery backup indicator output. Goes high when

power is drawn from an external battery.

PF0-PF7

31-38

I/O

Port F, PF0-7. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. Input to the PLD.

3. Latched address outputs.

4. As address A0-3 inputs in 80C51XA mode

5. As data bus port (D0-7) in non-multiplexed bus configuration

PG0-PG7 21-28

I/O

Port G, PG0-7. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. Latched address outputs.

GND

8,30,

49,50,

VCC

9,29,

Table 5.

PSD835G2

Descriptions

(cont.)

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