TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

23

POST OFFICE BOX 655303

APPLICATION INFORMATION

As with the isolation method described in the IEEE 1394-1995 standard, care must be taken to ensure that the

input and output are synchronized during power up of either the phy, LLC, or both. This can be accomplished

internally in some cases with the LREQ terminal. During power up reset the LREQ input of the phy can be pulled

low, which should also be the driving state of the LREQ output of the LLC device during power up. The LREQ

terminal has the potential of hanging the phy-LLC interface if the phy senses a high input while the LLC continues

driving low after a power up of either or both devices.

Another phy-LLC signal with the potential to cause problems when the states across the phy-LLC interface do

not match is the LPS signal. For instance, when attempting to pass the LPS signal in as a dc signal across a

bus-holder and capacitor-type isolation, there are challenges to be met. If the LLC powers up first, while the phy

was still powered down, the isolation capacitor could have a charge induced on it. In a 3-V system the LLC side

of the capacitor would be charged to 3 V while the phy side remained at ground potential. When the phy was

then powered up, the capacitor and the bus holder could keep the LPS input signal at the low level and the states

would not be synchronized. This would then cause the phy to disable all phy-LLC output terminals, and the node

could lock up. By transitioning the state the logic levels on each side of the capacitor, the states can be

synchronized. In the LPS example, a case has been hypothesized where the LLC side of the isolation capacitor

is logic high while the phy side is low. If the LLC then drives a low level, the phy side of the capacitor also tries

to swing the same voltage down . However since the phy side of the isolation capacitor is already in the low state,

the voltage goes negative until the clamping diode is turned on. This diode to ground clamps the voltage and

dissipates the charge on the capacitor bringing the state on each side of the isolating capacitor into

synchronization. For the dc-type signals, these transitions do not cause a loss of information. However for the

ac signals (i.e., LREQ) the first bit of the transmission is lost, making this method of achieving synchronization

only useful if a dummy transition of the signal can be generated and tolerated. A much better approach for the

LPS signal would be to use an ac signal across the bus holder and capacitor isolation. The TI physical-layer

device LPS terminal recognizes a square wave of between 220-kHz and 5.5-MHz as the signal that the LLC

is on. The generation of this square-wave signal would need to be designed such that whenever the LLC is

powered up, the signal is on. On the TSB12C01A and TSB12LV31 LLC devices, this signal is supplied as the

power on terminal (see Figure 13).

Bus

Holder

LLC

Phy

Power

On

LPS

0.001

µF

Figure 13. External Bus-Holder Implementation for AC LPS Line

Since the TSB12LV21 does not supply a square-wave signal, the system designer needs to provide either an

ac or dc signal to the phy if this feature is desired. A TIL191A optoisolator can provide a square-wave signal

in a dc form for slightly more than $0.30 a line (see Figure 14).