TSB12C01A datasheet(7/38 Pages) TI

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TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

TYPE

I/O

DESCRIPTION

NAME

NO.

TYPE

I/O

DESCRIPTION

PLLGND

52, 53

Supply

—

PLL circuit ground. The PLLGND terminals should be tied to the low-impedance circuit-board

ground plane.

PLLVDD

Supply

—

PLL circuit power. PLLVDD supplies power to the PLL portion of the device. It is recom-

mended that a combination of high-frequency decoupling capacitors be connected to

PLLVDD (i.e., paralleled 0.1 µF and 0.001 µF). Lower frequency 10-µF filtering capacitors

can also be used. These supply terminals are separated from AVDD and DVDD internally in

the device to provide noise isolation. These terminals should also be tied at a low-impedance

point on the circuit board. Individual filtering networks for each is desired.

—

Current setting resistor. An internal reference voltage is applied to a resistor connected be-

tween R0 and R1 to set the operating current and the cable driver output current. A low tem-

perature-coefficient resistor (TCR) 6.3 k

Ω ±5% resistor should be used to meet the IEEE

1394-1995 standard requirements for output voltage limits.

RESET

CMOS

Reset. When RESET is asserted low (active), a bus reset condition is set on the active cable

ports and the the internal logic is reset to the reset start state. An internal pullup resistor,

which is connected to VDD, is provided so only an external delay capacitor is required. This

input is a standard logic buffer and can also be driven by an open-drain logic output buffer.

The minimum hold time for RESET is listed in the recommended operating characteristics

table.

SYSCLK

CMOS

System clock. SYSCLK provides a 49.152-MHz clock signal, which is synchronized with the

data transfers to the LLC.

TESTM1

TESTM2

CMOS

Test mode control. TESTM1 and TESTM2 are used during the manufacturing test and

should be tied to VDD.

TPA1+

TPA2+

TPA3+

Cable

Portn, port cable pair A. TPAn is the port A connection to the twisted-pair cable. Board traces

from these terminals should be kept matched and as short as possible to the external load

TPA1–

TPA2–

TPA3–

Cable

from these terminals should be kept matched and as short as possible to the external load

resistors and to the cable connector.

TPB1+

TPB2+

TPB3+

Cable

Portn, port cable pair B. TPBn is the port B connection to the twisted-pair cable. Board traces

from these terminals should be kept matched and as short as possible to the external load

TPB1–

TPB2–

TPB3–

Cable

from these terminals should be ke t matched and as short as ossible to the external load

resistors and to the cable connector.

TPBIAS1

TPBIAS2

TPBIAS3

Cable

Portn, twisted-pair bias. TPBIASn provides the 1.86-V nominal bias voltage needed for prop-

er operation of the twisted-pair cable drivers and receivers and for sending a valid cable

connection signal to the remote nodes.

VDD–5V

Supply

—

5-V VDD supply. VDD–5V should be connected to the LLC VDD supply when a 5-V LLC is

connected to the phy, and it should be connected to the phy DVDD when a 3-V LLC is used.

—

Crystal oscillator. XO and XI connect to a 24.576-MHz parallel resonant fundamental mode

crystal. Although, when a 24.576-MHz crystal oscillator is used, it can be connected to XI

with XO left unconnected. The optimum values for the external shunt capacitors are depen-

dent on the specifications of the crystal used. The suggested values of 12 pF are appropriate

for a crystal with 15-pF specified loads.

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