TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

21

POST OFFICE BOX 655303

APPLICATION INFORMATION

There are several design challenges with transformer-isolation circuit of galvanic isolation barrier. They are:

component costs and board space.

must be added to each input buffer.

using CMOS-type input buffers, as much as a mA of supply current can be wasted in each input.

ground.

and hold time windows allowed for each input.

threshold level and the minimum hysteresis level on the high side and the difference between the minimum

threshold level and the maximum hysteresis level on the low side.

the input state are synchronized; in other words, ensure that the voltage levels on each side of the isolation

capacitor represent the same logic state. Input power-up glitches can cause output and input states to be

out of synchronization causing communication errors between the phy and the LLC. As data is passed

through the isolation barrier, the output and input eventually synchronize, but there is the possibility of

locking up the system before synchronization occurs.

Texas Instruments bus holder galvanic isolation barrier

Texas Instruments patent-pending bus-holder galvanic isolation technique simplifies most of the previously

mentioned design challenges. Bus-holder circuits are required on the input side (both sides when bidirectional)

of the single capacitor that forms the galvanic isolation barrier. The bus-hold function consists of a CMOS-buffer

stage with a high-resistance feedback path between its output and its input. This prevents bus lines from floating

without using pullup or pulldown resistors. The high-impedance inputs of these internal CMOS buffers are

connected to the input terminals of the device. The feedback path on the internal buffer stage keeps a bus line

tied to the bus holder at the last valid logic state generated by an active driver. Active bus-hold circuitry typically

holds unused or floating-data inputs at valid logic levels and eliminates the need for pullup or pulldown resistors.

These bus holders can be integrated into the phy and LLC devices at extremely low cost. If either the phy, the

LLC, or both does not have the bus holders integrated, external bus holders can be implemented. Bus holder

ICs or ICs with bus-holder inputs are available commercially that are capable of performing this function. TI

plans to integrate bus holders internally on future revisions of its phys and LLCs. Figure 12 shows a typical

implementation using phy and LLC devices with internal bus holders.