TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

13

POST OFFICE BOX 655303

APPLICATION INFORMATION

Table 2. Internal Register Field Descriptions (continued)

FIELD

SIZE

TYPE

DESCRIPTION

CPS

1

Read

only

Cable power status (CPS) contains the status of the CPS input terminal. When cable power voltage has

dropped too low for reliable operation, CPS is reset (0). CPS is included twice in the internal registers to

expedite handling of the CPSInt.

CPSInt

1

Read/

Write

CPSint indicates that a cable power status interrupt has occurred. This interrupt occurs whenever the CPS

input goes low. The interrupt indicates that the cable power voltage has dropped too low to ensure reliable op-

eration. This bit is cleared (0) by a hardware reset or by writing a 0 to this register. However, if the CPS input

is still low, another cable-power status interrupt immediately occurs.

GC

6

Read/

Write

The gap count (GC) register sets the fair and arb-reset gap times. The gap count may be set to a particular

value to optimize bus performance. Typically, the gap count should be set to 2 times the maximum number

of hops on the bus and should be set to the same value for all nodes on the bus. The gap count can be set

by either a write to this register or by reception or transmission of a PHY_CONFIG packet. The gap count

is reset to 3Fh after a hardware reset or after two consecutive bus resets without an intervening write to

the gap count register (either a write to the gap count register by the LLC or a PHY_CONFIG packet).

IBR

1

Read/

Write

When set, initiate bus reset (IBR) causes the current node to immediately initiate a bus reset. IBR is

cleared (0) after a hardware reset or a bus reset.

IR

1

Read/

Write

IR indicates that the last bus reset was initiated in this TSB21LV03 phy. This bit is also included in the Self-

ID packet.

LoopInt

1

Read/

Write

LoopInt indicates that a configuration loop timeout has occurred. This interrupt occurs when the arbitration

controller waits for too long a period of time during tree-ID. This interrupt can indicate that the bus is con-

figured in a loop. This bit is cleared (0) by a hardware reset or by writing a 0 to this register bit.

NP

4

Read

only

NP contains the number of ports implemented in the core logic (not the number of ports actually on the

device). For the TSB21LV03, NP is set to 0011b.

Physical ID

6

Read

only

Physical ID contains the physical address of the local node. The physical ID defaults to 09h after a hard-

ware reset or a bus reset until the Self-ID process has been completed. A complete Self-ID is indicated by

an unsolicited status transfer of the register 0 contents to the LLC.

R

1

Read

only

R indicates whether the current node is the root node or not. This bit is cleared (0) on a hardware reset or

a bus reset. This bit is set during tree-ID when the current node is root.

Rev

2

Read

only

The revision (Rev) bits indicate the design revision of the core logic. For the TSB21LV03, Rev is set to 00.

RHB

1

Read/

Write

When set, the root hold-off bit (RHB) instructs the local node to try to become the root node during the next

bus reset. RHB is reset (0) during a hardware reset and is not affected by a bus reset.

SPD

2

Read

only

The speed (SPD) bits indicates the top signaling speed of the local port and for the TSB21LV03 is set to

01b.