MK68564 datasheet(30/46 Pages) STMICROELECTRONICS

30 / 46 page

terminated, or at the beginning of CRC transmission

when the Transmit Underrun/EOM latch in Status

ternal/Status interrupts will occur.

If this bit is set when an External/Status condition is

pending, an interrupt will be requested. It is re-

commended that a Reset External/Status Interrupts

command (Command 2 in the Command Register)

be issued prior to enabling External/Status inter-

rupts.

SYNC WORD REGISTER 1 (SYNC 1)

This register is programmed to contain the transmit

sync character in the Monosync mode, the first eight

bits of the 16-bit sync character in the Bysinc mode,

or the transmit sync character in the External Sync

mode. This register is not used in Asynchronous

mode. In the SDLC mode, this register is program-

med to contain the secondary address field used to

compare against the address field of the SDLC

frame. The SIO does not automatically transmit the

station address at the beginning of a response

frame. This register is reset to ”00H” by a channel

or hardware reset.

SYNC WORD REGISTER 2 (SYNC 2)

This register is programmed to contain the receive

sync character in the Monosync mode, the last eight

bits of the 16-bit sync character in the Bisync mode,

or a flag character (01111110) in the SDLC mode.

This register is not used in the External Sync mode

and the Asynchronous mode. This register is reset

to ”00H” by a channel or hardware reset.

RECEIVER CONTROL REGISTER

(RCVCTL)

This register contains the control bits and parame-

ters for the receiver logic. This register is reset to

”00H” by a channel or hardware reset.

D7, D6 : Receiver Bits/Character 1 and 0

The state of these two bits determines the number

of bits to be assembled as a character in the recei-

ved serial data stream. If Parity is enabled, one ad-

ditional bit will be added to each character. The num-

ber of bits per character can be changed while a

character is being assembled but only before the

number of bits currently programmed is reached. All

data is right-justified in the shift register and trans-

ferred to the receive data FIFO in 8-bit groups.

In Asynchronous mode, transfers are made at char-

acter boundaries, and all unused bits of character

are set to a one. In Synchronous modes and SDLC

mode, an 8-bit segment of the serial data stream is

transferred to the data FIFO when the internal coun-

ter reaches the number of bits per character pro-

grammed. For less than eight bits per character, no

parity, the MSB bit(s) of the first transfer will be the

LSB bit(s) of the next transfer.

D5 : Receiver Auto Enables

When this bit is set to a one, and the Receiver Ena-

ble bit is also set, a Low on the DCD input pin be-

comes the enable for the receiver. When this bit is

zero, the DCD pin is simply an input to the SIO, and

its status is displayed in Status Register 0.

D4 : Enter Hunt Mode

This bit, when written to a one, rearms the receiver

synchronization logic and forces the comparison of

the received bit stream to the ontents of Sync Word

upon which Synchronous mode is selected, until bit

synchronization is achieved. The SIO automatically

enters the Hunt mode after a channel or hardware

reset, after an Abort condition is detected, or when

the receiver is disabled. When the Hunt mode is en-

tered, the Hunt/Sync bit in Status Register 0 is set

to a one. When synchronization is achieved, the

Hunt/Sync bit is reset to a zero. If External/Status in-

terrupts are enabled, an interrupt request will be ge-

nerated on both transitions of the Hunt/Sync bit. En-

ter Hunt Mode has no affect in Asynchronous

modes. This bit is not latched and will always be read

as a zero.

D 6

D 4

D 2

SYNC/

SDLC7

SYNC/

SDLC6

SYNC/

SDLC5

SYNC/

SDLC4

SYNC/

SDLC3

SYNC/

SDLC2

SYNC/

SDLC1

SYNC/

SDLC0

D 6

D 4

SYNC/

SDLC

SYNC/

SDLC

SYNC/

SDLC

SYNC/

SDLC

SYNC/

SDLC

SYNC/

SDLC

SYNC/

SDLC

SYNC/

SDLC 8

RX BITS

CHAR 1

RX BITS

CHAR 0

Bits/character

(no parity)

Bits/character

(parity)

D 7

D 6

D 4

D 0

RX BITS

CHAR 1

RX BITS

CHAR 0

RX AUT O

ENAB.

H UNT

MO DE

RX CRC

ENAB.

ADDR.

STRIP

SYNC

ENABLE

MK68564

30/46

MK68564 датащи(PDF) 30 Page - STMicroelectronics

MK68564 датащи(HTML) 30 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

датащи скачать

ссылки URL