MK68564 datasheet(28/46 Pages) STMICROELECTRONICS

28 / 46 page

D5, D4 : Sync Modes 1 and 0

These bits select the various options for character

synchronization. These bits are ignored, unless

Sync modes is selected in the Stop Bits filed of this

D3, D2 : Stop Bits 1 and 0

These bits determine the number of stop bits added

to each Asynchronous character that is transmitted.

The receiver always checks for one stop bit in Asyn-

chronous mode. A special code (00) signifies that a

Synchronous mode is to be selected. 1 1/2 stop bits

is not allowed if x1 clock rate is selected, because it

will lock up the transmitter.

D1 : Parity Even/Odd

If the Parity Enable bit is set, this bit determines whe-

ther parity is checked as even or as odd. (1 = even,

0 = odd). This bit is ignored if the Parity Enable bit

is reset.

D0 : Parity Enable

If this bit is set to a one, one additional bit position

beyond those specified in the bits/character control

field is added to the transmitted data and is expected

in the receive data. The received parity bit is trans-

ferred to the CPU as part of the data character, un-

less eight bits per character is selected in the Recei-

ver Control Register.

INTERRUPT CONTROL REGISTER

(INTCTL)

This register contains the control bits for the various

interrupt modes and the DMA handshaking signals.

This register is reset to ”00H” by a channel or hard-

ware reset.

D7 : CRC-16/SDLC-CRC

This bit selects the CRC polynomial used by both the

transmitter and receiver. When set to a one, the

CRC-16 polynomial (x16 + x15 + x2 + 1) is used ;

when reset to a zero, the SDLC-CRC polynomial

(x16 + x12 + x5 + 1) is used. If the SDLC mode is

selected, the CRC generator and checker are preset

to all ones and a special check sequence is used.

The SDLC-CRC polynomial must be selected in

SDLC mode. Failure to do so will result in receiver

CRC errors. When a Synchronous mode, other than

SDLC, is selected, the CRC generator and checker

are preset to all zeros (for both polynomials). This bit

must be programmed before CRC is enabled in the

receiver and transmitter control registers, to assure

valid CRC generation and checking. This bit is igno-

red in Asynchronous modes.

D6 : Tx Ready Enable

When this bit is set to a one, the TxRDY output pin

will pulse Low for three clock cycles (CLK) when the

transmit buffer becomes empty. When this bit is ze-

ro, the TxRDY pin is held High.

D5 : Rx Ready Enable

When this bit is set to a one, the TxRDY output pin

will pulse Low for three clockcycles (CLK) when a

character is available in the receive buffer. If a Spe-

cial Receive Condition is detected when the Re-

ceive Interrupt On FIrst Character Only interrupt

mode is selected, the RxRDY pin will not become

active ; instead, a special Receive Condition inter-

rupt will be generated. When this bit is zero, the

RxRDY pin will be held High

SYNC

MODE 1

SYNC

MODE 0

8-bit Programmed Sync

16-bit Programmed Sync

SDLC Mode (01111110 flag

pattern)

External Sync Mode

STO P

BIT 1

STO P

BIT 0

Sync Modes

1 Stop Bit per Character

11/2 Stop Bits per Character

2 Stop Bits per Character

D 6

D 2

D 1

D 0

CRC16/

SDLC

CTX

RDY

ENABLE

RX RDY

ENABLE

RX INT

MODE

RX INT

MODE

STATUS

AFFECTS

TX INT

ENABLE

EXT INT

ENABLE

CLO CK

RATE 1

CLO CK

RATE 0

Multiple

x16

x32

x64

Clock Rate = Data Rate

Clock Rate = 16 x Data

Rate

Clock Rate = 32 x Data

Rate

Clock Rate = 64 x Data

Rate

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