MK68564 datasheet(14/46 Pages) STMICROELECTRONICS

14 / 46 page

Figure 9 : Asynchronous Message Format.

V000382

The SIO provides five I/O lines that may be used for

modem control, for external interrupts, or as general

purpose I/O. The Request To Send (RTS) and Data

Terminal Ready (DTR) pins are outputs that follow

the inverted state of their respective bits in the

Transmitter Control Register. The RTS pin can also

be used to signal the end of a message in Asynchro-

nous modes, as explained below in the transmitter

section. The Data Carrier Detect (DCD), Clear To

Send (CTS), and SYNC pins are inputs to the SIO

in Asynchronous modes. DCD and CTS can be u-

sed as auto enables to the receiver and transmitter,

respectively, or if External/Status Interrupts are en-

abled all three input pins will be monitored for a

change of status. If these inputs change for a period

of time greater than the minimum specified pulse

width, an interrupt will be generated.

In the following discussion, all interrupt modes are

assumed enabled.

ASYNCHRONOUS TRANSMIT

Start of Transmission. The SIO will start transmit-

ting data when the Transmit Enable bit is set to a

one, and a character has been loaded into the trans-

mit buffer. If the TxAuto Enables bit is set, the SIO

will wait for a Low on the Clear To Send input (CTS)

before starting data transmission. The Tx Auto En-

ables feature allows the programmer to send the

first data character of the message to the SIO wi-

thout waiting for CTS to go Low. In all cases, the

Transmit Enable bit must be set before transmission

can begin. The transitions on the CTS pin will gene-

rate External/Status interrupt requests and also

latch up the external/status logic. The external/sta-

tus logic should be rearmed by issuing a Reset Ex-

ternal/Status Interrupts command.

Transmit Characteristics. The SIO automatically

inserts a start bit, the programmed parity bit (odd, e-

ven, or no parity), and the programmed number of

stop bits to the data character to be transmitted. The

transmitter can transmit from one to eight data bits

per character. All characters are transmitted least-

significant bit first. When the character length pro-

grammed is six or seven bits, the unused bits of the

transmit buffer are automatically ignored. When a

character length of five bits or less is programmed,

the data loaded into the transmit buffer must be for-

matted as described in the Transmitter Control Re-

gister part of the Register Description section. Serial

data is shifted out of the TxD pin on the falling edge

of the Transmit Clock (TxC) at a rate equal to 1,

1/16th, 1/32nd, or 1/64th of TxC.

Data Transfer. The SIO will signal the CPU or other

bus master with a transmit interrupt request and set

the Tx Buffer Empty bit in Status Register 0, every

time the contents of the transmit buffer are loaded

into the transmit shift register. The interrupt request

will be cleared when a new character is loaded into

the transmit buffer, or a Reset Tx Interrupt Pending

command (Command 5) is issued. If Command 5 is

issued, the transmit buffer will have to be loaded be-

fore any additional transmit interrupt requests are

generated. The Tx Buffer Empty bit is reset when a

new character is loaded into the transmit buffer.

The All Sent bit in Status Register 1 is used to indi-

cate when all data in the shift register has been

transmitted, and the transmit buffer is empty. This bit

is Low, while the transmitter is sending characters,

and it will go High one bit time after the transmit clock

that clocks out the last stop bit of the character on

the TxD pin. No interrupts are generated by the All

Sent bit transitions. The Request To Send (RTS) bit

MK68564

14/46

MK68564 датащи(PDF) 14 Page - STMicroelectronics

MK68564 датащи(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

датащи скачать

ссылки URL