ADSP-21990BBC datasheet(7/50 Pages) AD

7 / 50 page

ADSP-21990

Rev. A

Page 7 of 50

August 2007

devices connected to the external memory interface. DMA

capable peripherals include the SPORT and SPI ports, and ADC

control module. Each individual DMA capable peripheral has a

dedicated DMA channel. To describe each DMA sequence, the

DMA controller uses a set of parameters—called a DMA

descriptor. When successive DMA sequences are needed, these

DMA descriptors can be linked or chained together, so the com-

pletion of one DMA sequence autoinitiates and starts the next

sequence. DMA sequences do not contend for bus access with

the DSP core, instead DMAs “steal” cycles to access memory.

All DMA transfers use the DMA bus shown in Figure 2 on

Page 4. Because all of the peripherals use the same bus, arbitra-

tion for DMA bus access is needed. The arbitration for DMA

bus access appears in Table 1.

DSP PERIPHERALS ARCHITECTURE

The ADSP-21990 contains a number of special purpose, embed-

ded control peripherals, which can be seen in the functional

block diagram on Page 1. The ADSP-21990 contains a high per-

formance, 8-channel, 14-bit ADC system with dual-channel

simultaneous sampling ability across four pairs of inputs. An

internal precision voltage reference is also available as part of

the ADC system. In addition, a 3-phase, 16-bit, center-based

PWM generation unit can be used to produce high accuracy

PWM signals with minimal processor overhead.

The ADSP-21990 also contains a flexible incremental encoder

interface unit for position sensor feedback; two adjustable fre-

quency auxiliary PWM outputs, 16 lines of digital I/O; a

16-bit watchdog timer; three general-purpose timers, and an

interrupt controller that manages all peripheral interrupts.

Finally, the ADSP-21990 contains an integrated power-on-reset

(POR) circuit that can be used to generate the required reset sig-

nal for the device on power-on.

The ADSP-21990 has an external memory interface that is

shared by the DSP core, the DMA controller, and DMA capable

peripherals, which include the ADC, SPORT, and SPI commu-

nication ports. The external port consists of a 16-bit data bus, a

20-bit address bus, and control signals. The data bus is config-

urable to provide an 8- or 16-bit interface to external memory.

Support for word packing lets the DSP access 16- or 24-bit

words from external memory regardless of the external data

bus width.

The memory DMA controller lets the ADSP-21990 move data

and instructions from between memory spaces: internal-to-

external, internal-to-internal, and external-to-external. On-chip

peripherals can also use this controller for DMA transfers.

The embedded ADSP-21xx core can respond to up to 17 inter-

rupts at any given time: three internal (stack, emulator kernel,

and power down), two external (emulator and reset), and 12

user-defined (peripherals) interrupts. Programmers assign each

of the 32 peripheral interrupt requests to one of the 12 user

defined interrupts. These assignments determine the priority of

each peripheral for interrupt service.

The following sections provide a functional overview of the

ADSP-21990 peripherals.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The serial peripheral interface (SPI) port provides functionality

for a generic configurable serial port interface based on the SPI

standard, which enables the DSP to communicate with multiple

SPI-compatible devices. Key features of the SPI port are:

• Interface to host microcontroller or serial EEPROM.

• Master or slave operation (3-wire interface MISO, MOSI,

SCK).

•Data rates to HCLK 4 (16-bit baud rate selector).

• 8- or 16-bit transfer.

• Programmable clock phase and polarity.

• Broadcast Mode-1 master, multiple slaves.

• DMA capability and dedicated interrupts.

• PF0 can be used as slave select input line.

• PF1–PF7 can be used as external slave select output.

SPI is a 3-wire interface consisting of two data pins (MOSI and

MISO), one clock pin (SCK), and a single slave select input

(SPISS) that is multiplexed with the PF0 flag I/O line and seven

slave select outputs (SPISEL1 to SPISEL7) that are multiplexed

with the PF1 to PF7 flag I/O lines. The SPISS input is used to

select the ADSP-21990 as a slave to an external master. The

SPISEL1 to SPISEL7 outputs can be used by the ADSP-21990

(acting as a master) to select/enable up to seven external slaves

in a multidevice SPI configuration. In a multimaster or a multi-

device configuration, all MOSI pins are tied together, all MISO

pins are tied together, and all SCK pins are tied together.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on the serial data

line. The serial clock line synchronizes the shifting and sam-

pling of data on the serial data line.

In master mode, the DSP core performs the following sequence

to set up and initiate SPI transfers:

• Enables and configures the SPI port operation (data size

and transfer format).

• Selects the target SPI slave with the SPISELx output pin

(reconfigured programmable flag pin).

• Defines one or more DMA descriptors in Page 0 of I/O

memory space (optional in DMA mode only).

• Enables the SPI DMA engine and specifies transfer direc-

tion (optional in DMA mode only).

• In nonDMA mode only, reads or writes the SPI port

receive or transmit data buffer.

Table 1. I/O Bus Arbitration Priority

DMA Bus Master

Arbitration Priority

SPORT Receive DMA

0—Highest

SPORT Transmit DMA

ADC Control DMA

SPI Receive/Transmit DMA

Memory DMA

4—Lowest

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