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ADSP-21990BBC датащи(PDF) 28 Page - Analog Devices |
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ADSP-21990BBC датащи(HTML) 28 Page - Analog Devices |
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28 / 50 page ![]() Rev. A | Page 28 of 50 | August 2007 ADSP-21990 External Port Write Cycle Timing Table 9 and Figure 10 describe external port write operations. The external port lets systems extend read/write accesses in three ways: wait states, ACK input, and combined wait states and ACK. To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP to wait, and the DSP requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter in the ADSP-2199x Mixed Signal DSP Controller Hard- ware Reference. Table 9. External Port Write Cycle Timing Parameter Min Max Unit Timing Requirements 1, 2 tAKW ACK Strobe Pulse Width 12.5 ns tDWSAK ACK Delay from XMS Low 0.5tEMICLK – 1 ns Switching Characteristics tCSWS Chip Select Asserted to WR Asserted Delay 0.5tEMICLK – 4 ns tAWS Address Valid to WR Setup and Delay 0.5tEMICLK – 3 ns tWSCS WR Deasserted to Chip Select Deasserted 0.5tEMICLK – 4 ns tWSA WR Deasserted to Address Invalid 0.5tEMICLK – 3 ns tWW WR Strobe Pulse Width tEMICLK–2 + W 3 ns tCDA WR to Data Enable Access Delay 0 ns tCDD WR to Data Disable Access Delay 0.5tEMICLK – 3 0.5tEMICLK + 4 ns tDSW Data Valid to WR Deasserted Setup tEMICLK + 1 + W 3 tEMICLK + 7 + W 3 ns tDHW WR Deasserted to Data Invalid Hold Time; E_WHC 4, 5 3.4 ns tDHW WR Deasserted to Data Invalid Hold Time; E_WHC4, 6 tEMICLK + 3.4 ns tWWR WR Deasserted to WR, RD Asserted tHCLK ns 1 tEMICLK is the external memory interface clock period. tHCLK is the peripheral clock period. 2 These are timing parameters that are based on worst-case operating conditions. 3 W = (number of wait states specified in wait register) tBMCLK 4 Write hold cycle–memory select control registers (MS CTL). 5 Write wait state count (E_WHC) = 0 6 Write wait state count (E_WHC) = 1 |
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