ADSP-21990BBC datasheet(6/50 Pages) AD

6 / 50 page

Rev. A

Page 6 of 50

August 2007

ADSP-21990

the external memory access strobe widths. For more informa-

tion, see Clock Signals on Page 12. The off-chip memory

spaces are:

• External memory space (MS3–0 pins)

• I/O memory space (IOMS pin)

• Boot memory space (BMS pin)

All of the above off-chip memory spaces are accessible through

the external port, which can be configured for 8-bit or 16-bit

data widths.

External Memory Space

External memory space consists of four memory banks. These

banks can contain a configurable number of 64 K word pages.

At reset, the page boundaries for external memory have Bank0

containing Pages 1 to 63, Bank1 containing Pages 64 to 127,

Bank2 containing Pages 128 to 191, and Bank3 containing Pages

192 to 254. The MS3-0 memory bank pins select Banks 3-0,

respectively. Both the ADSP-2199x core and DMA capable

peripherals can access the DSP external memory space.

All accesses to external memory are managed by the external

memory interface unit (EMI).

I/O Memory Space

The ADSP-21990 supports an additional external memory

called I/O memory space. The I/O space consists of 256 pages,

each containing 1024 addresses. This space is designed to sup-

port simple connections to peripherals (such as data converters

and external registers) or to bus interface ASIC data registers.

The first 32K addresses (I/O Pages 0 to 31) are reserved for

on-chip peripherals. The upper 224K addresses (I/O Pages 32 to

255) are available for external peripheral devices. External I/O

pages have their own select pin (IOMS). The DSP instruction set

provides instructions for accessing I/O space.

Boot Memory Space

Boot memory space consists of one off-chip bank with 254

pages. The BMS memory bank pin selects boot memory space.

Both the ADSP-2199x core and DMA capable peripherals can

access the DSP off-chip boot memory space. After reset, the

DSP always starts executing instructions from the on-chip

boot ROM.

BUS REQUEST AND BUS GRANT

The ADSP-21990 can relinquish control of the data and address

buses to an external device. When the external device requires

access to the bus, it asserts the bus request (BR) signal. The (BR)

signal is arbitrated with core and peripheral requests. External

bus requests have the lowest priority. If no other internal

request is pending, the external bus request will be granted. Due

to synchronizer and arbitration delays, bus grants will be pro-

vided with a minimum of three peripheral clock delays. The

ADSP-21990 will respond to the bus grant by:

• Three-stating the data and address buses and the MS3–0,

BMS, IOMS, RD, and WR output drivers.

• Asserting the bus grant (BG) signal.

The ADSP-21990 will halt program execution if the bus is

granted to an external device and an instruction fetch or data

read/write request is made to external general-purpose or

peripheral memory spaces. If an instruction requires two exter-

nal memory read accesses, the bus will not be granted between

the two accesses. If an instruction requires an external memory

read and an external memory write access, the bus may be

granted between the two accesses. The external memory inter-

face can be configured so that the core will have exclusive use of

the interface. DMA and bus requests will be granted. When the

external device releases BR, the DSP releases BG and continues

program execution from the point at which it stopped.

The bus request feature operates at all times, even while the DSP

is booting and RESET is active.

The ADSP-21990 asserts the BGH pin when it is ready to start

another external port access, but is held off because the bus was

previously granted. This mechanism can be extended to define

more complex arbitration protocols for implementing more

elaborate multimaster systems.

DMA CONTROLLER

The ADSP-21990 has a DMA controller that supports auto-

mated data transfers with minimal overhead for the DSP core.

Cycle stealing DMA transfers can occur between the

ADSP-21990 internal memory and any of its DMA capable

peripherals. Additionally, DMA transfers can be accomplished

between any of the DMA capable peripherals and external

Figure 4. I/O Memory Map

ON-CHIP

PERIPHERALS

16-BITS

OFF-CHIP

PERIPHERALS

16-BITS

PAGES 0 TO 31

1024 WORDS/PAGE

2 PERIPHERALS/PAGE

0x00::0x000

0x20::0x000

0xFF::0x3FF

0x1F::0x3FF

PAGES 32 TO 255

1024 WORDS/PAGE

Figure 5. Boot Memory Map

PAGES 1 TO 254

64K WORDS/PAGE

0x01 0000

0xFE 0000

OFF-CHIP

BOOT MEMORY

16-BITS

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