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TMS320DM641 датащи(PDF) 91 Page - Texas Instruments |
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TMS320DM641 датащи(HTML) 91 Page - Texas Instruments |
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91 / 179 page ![]() Enhanced Direct Memory Access (EDMA) Controller 91 June 2003 − Revised October 2005 SPRS222E Table 4−3. TMS320DM641/DM640 EDMA Channel Synchronization Events† EDMA CHANNEL EVENT NAME EVENT DESCRIPTION 0 DSP_INT HPI-to-DSP interrupt [For DM641 Only; “None” for DM640] 1 TINT0 Timer 0 interrupt 2 TINT1 Timer 1 interrupt 3 SD_INTA EMIFA SDRAM timer interrupt 4 GPINT4/EXT_INT4 GP0 event 4/External interrupt pin 4 5 GPINT5/EXT_INT5 GP0 event 5/External interrupt pin 5 6 GPINT6/EXT_INT6 GP0 event 6/External interrupt pin 6 7 GPINT7/EXT_INT7 GP0 event 7/External interrupt pin 7 8 GPINT0 GP0 event 0 9 GPINT1 GP0 event 1 10 GPINT2 GP0 event 2 11 GPINT3 GP0 event 3 12 XEVT0 McBSP0 transmit event 13 REVT0 McBSP0 receive event 14 XEVT1 McBSP1 transmit event 15 REVT1 McBSP1 receive event 16 VP0EVTYA VP0 Channel A Y event DMA request 17 VP0EVTUA VP0 Channel A Cb event DMA request 18 VP0EVTVA VP0 Channel A Cr event DMA request 19 TINT2 Timer 2 interrupt 20−31 – None 32 AXEVTE0 McASP0 transmit even event 33 AXEVTO0 McASP0 transmit odd event 34 AXEVT0 McASP0 transmit event 35 AREVTE0 McASP0 receive even event 36 AREVTO0 McASP0 receive odd event 37 AREVT0 McASP0 receive event 38−43 – None 44 ICREVT0 I2C0 receive event 45 ICXEVT0 I2C0 transmit event 46−47 – None 48 GPINT8 GP0 event 8 49 GPINT9 GP0 event 9 50 GPINT10 GP0 event 10 51 GPINT11 GP0 event 11 52 GPINT12 GP0 event 12 53 GPINT13 GP0 event 13 54 GPINT14 GP0 event 14 55 GPINT15 GP0 event 15 56 VP1EVTYA VP1 Channel A Y event DMA request [For DM641 Only; “None” for DM640] † In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234). |
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