TMS320DM641 datasheet(84/179 Pages) TI

84 / 179 page

DM641/DM640 Peripheral Information and Electrical Specifications

June 2003 − Revised October 2005

SPRS222E

DM641/DM640 Peripheral Information and Electrical Specifications

4.1

Parameter Information

4.1.1

Parameter Information Device-Specific Information

Transmission Line

4.0 pF

1.85 pF

Z0 = 50 Ω

(see note)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output

Under

Test

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects

must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.

The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from

the data sheet timings.

42 Ω

3.5 nH

Device Pin

(see note)

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 4−1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This

load capacitance value does not indicate the maximum load the device is capable of driving.

4.1.1.1

Signal Transition Levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

Vref = 1.5 V

Figure 4−2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX

and VOH MIN for output clocks.

Vref = VIL MAX (or VOL MAX)

Vref = VIH MIN (or VOH MIN)

Figure 4−3. Rise and Fall Transition Time Voltage Reference Levels

4.1.1.2

Signal Transition Rates

All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).

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