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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM641 датащи(PDF) 44 Page - Texas Instruments |
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TMS320DM641 датащи(HTML) 44 Page - Texas Instruments |
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44 / 179 page  Pin Assignments 44 June 2003 − Revised October 2005 SPRS222E Table 1−6. Terminal Functions (Continued) SIGNAL TYPE† IPD/ DESCRIPTION NAME DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS RESET P4 P4 I Device reset NMI B4 B4 I IPD Nonmaskable interrupt, edge-driven (rising edge) Note: Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is recommended that the NMI pin be grounded versus relying on the IPD. GP0[7]/EXT_INT7 E1 E1 I/O/Z IPU General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (it l ) Th d f l f i i GPIO bl d i l GP0[6]/EXT_INT6 F2 F2 I/O/Z IPU pp p p ( ) p ( )p (input only). The default after reset setting is GPIO enabled as input-only. • When these pins function as External Interrupts [by selecting the GP0[5]/EXT_INT5 F3 F3 I/O/Z IPU • When these pins function as External Interrupts [by selecting the corresponding interrupt enable register bit (IER.[7:4])], they are edge driven and the polarity can be independently selected via the GP0[4]/EXT_INT4 F4 F4 I/O/Z IPU edge-driven and the polarity can be independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]). GP0[3] L5 L5 I/O/Z IPD The general-purpose 0 pin (GP0[3]) (I/O/Z). GP0[0] M5 M5 I/O/Z IPD GP0 0 pin (I/O/Z) [default] This pin can be programmed as GPIO 0 (input only) [default] or as GP0[0] (output only) pin or output as a general-purpose interrupt (GP0INT) signal (output only). Note: This pin must remain low during device reset. CLKOUT6/ GP0[2]§ C6 C6 I/O/Z IPU Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 2 pin (I/O/Z). CLKOUT4/ GP0[1]§ D6 D6 I/O/Z IPU Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 1 pin (I/O/Z). HOST-PORT INTERFACE (HPI) [DM641 ONLY] HINT N4 — I/O/Z Host interrupt from DSP to host (O) [default] HCNTL1 P1 — I/O/Z Host control − selects between control, address, or data registers (I) [default] HCNTL0 R3 — I/O/Z Host control − selects between control, address, or data registers (I) [default] HHWIL N3 — I/O/Z Host half-word select − first or second half-word (not necessarily high or low order) [For HPI16 bus width selection only] (I) [default] HR/W M1 — I/O/Z Host read or write select (I) [default] HAS P3 — I/O/Z Host address strobe (I) [default] HCS R1 — I/O/Z Host chip select (I) [default] HDS1 R2 — I/O/Z Host data strobe 1 (I) [default] HDS2 T2 — I/O/Z Host data strobe 2 (I) [default] HRDY N1 — I/O/Z Host ready from DSP to host (O) [default] † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. |
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