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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM641 датащи(PDF) 88 Page - Texas Instruments |
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TMS320DM641 датащи(HTML) 88 Page - Texas Instruments |
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88 / 179 page  Power Supplies 88 June 2003 − Revised October 2005 SPRS222E 4.3.4 Peripheral Power-Down Operation The DM641/DM640 device can be powered down in three ways: • Power-down due to pin configuration • Power-down due to software configuration − relates to the default state of the peripheral configuration bits in the PERCFG register. • Power-down during run-time via software configuration On the DM641/DM640 device, the EMAC and MDIO peripherals are controlled (selected) at the pin level during chip reset (e.g., using the MAC_EN pin). The McASP0, McBSP0, McBSP1, VP0, VP1 [DM641 only], and I2C0 peripheral functions are selected via the peripheral configuration (PERCFG) register bits. For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the Device Configurations section of this document. 4.3.5 Power-Down Modes Logic Figure 4−8 shows the power-down mode logic on the DM641/DM640. PWRD Internal Clock Tree CPU IFR IER CSR PD1 PD2 Power- Down Logic Clock PLL CLKIN RESET CLKOUT6 PD3 Internal Peripherals CLKOUT4 Clock and Dividers Distribution † External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic. TMS320DM641/DM640 Figure 4−8. Power-Down Mode Logic† |
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