AT91SAM7S64 datasheet(37/42 Pages) ATMEL

37 / 42 page

6175BS–ATARM–04-Nov-05

AT91SAM7S Series Summary

11.6

Two-wire Interface

• Master Mode only

• Compatibility with standard two-wire serial memories

• One, two or three bytes for slave address

• Sequential read/write operations

11.7

USART

• Programmable Baud Rate Generator

• 5- to 9-bit full-duplex synchronous or asynchronous serial communications

– 1, 1.5 or 2 stop bits in Asynchronous Mode

– 1 or 2 stop bits in Synchronous Mode

– Parity generation and error detection

– Framing error detection, overrun error detection

– MSB or LSB first

– Optional break generation and detection

– By 8 or by 16 over-sampling receiver frequency

– Hardware handshaking RTS - CTS

– Modem Signals Management DTR-DSR-DCD-RI on USART1 (not present on

AT91SAM7S32)

– Receiver time-out and transmitter timeguard

– Multi-drop Mode with address generation and detection

– Manchester Encoder/Decoder on AT91SAM7S256/128

• RS485 with driver control signal

• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards

– NACK handling, error counter with repetition and iteration limit

• IrDA modulation and demodulation

– Communication at up to 115.2 Kbps

• Test Modes

– Remote Loopback, Local Loopback, Automatic Echo

11.8

Serial Synchronous Controller

• Provides serial synchronous communication links used in audio and telecom applications

• Contains an independent receiver and transmitter and a common clock divider

• Offers a configurable frame sync and data length

• Receiver and transmitter can be programmed to start automatically or on detection of

different event on the frame sync signal

• Receiver and transmitter include a data signal, a clock signal and a frame synchronization

signal

11.9

Timer Counter

• Three 16-bit Timer Counter Channels

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