AT91SAM7S64 datasheet(28/42 Pages) ATMEL

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6175BS–ATARM–04-Nov-05

AT91SAM7S Series Summary

– Higher priority interrupts can be served during service of lower priority interrupt

• Vectoring

– Optimizes interrupt service routine branch and execution

– One 32-bit vector register per interrupt source

– Interrupt vector register reads the corresponding current interrupt vector

•Protect Mode

– Easy debugging by preventing automatic operations

•Fast Forcing

– Permits redirecting any interrupt source on the fast interrupt

• General Interrupt Mask

– Provides processor synchronization on events without triggering an interrupt

10.6

Debug Unit

• Comprises:

– One two-pin UART

– One Interface for the Debug Communication Channel (DCC) support

– One set of Chip ID Registers

– One Interface providing ICE Access Prevention

•Two-pin UART

– Implemented features are compatible with the USART

– Programmable Baud Rate Generator

– Parity, Framing and Overrun Error

– Automatic Echo, Local Loopback and Remote Loopback Channel Modes

• Debug Communication Channel Support

– Offers visibility of COMMRX and COMMTX signals from the ARM Processor

• Chip ID Registers

– Identification of the device revision, sizes of the embedded memories, set of

peripherals

– Chip ID is 0x270B0940 for AT91SAM7S256 (VERSION 0)

– Chip ID is 0x270A0740 for AT91SAM7S128 (VERSION 0)

– Chip ID is 0x27090540 for AT91SAM7S64 (VERSION 0)

– Chip ID is 0x27080342 for AT91SAM7S321 (VERSION 0)

– Chip ID is 0x27080340 for AT91SAM7S32 (VERSION 0)

10.7

Periodic Interval Timer

• 20-bit programmable counter plus 12-bit interval counter

10.8

Watchdog Timer

• 12-bit key-protected Programmable Counter running on prescaled SCLK

• Provides reset or interrupt signals to the system

• Counter may be stopped while the processor is in debug state or in idle mode

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