AT91SAM7S64 datasheet(27/42 Pages) ATMEL

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6175BS–ATARM–04-Nov-05

AT91SAM7S Series Summary

10.4

Power Management Controller

The Power Management Controller uses the Clock Generator outputs to provide:

• the Processor Clock PCK

• the Master Clock MCK

• the USB Clock UDPCK (not present on AT91SAM7S32)

• all the peripheral clocks, independently controllable

• three programmable clock outputs

The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating fre-

quency of the device.

The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing

reduced power consumption while waiting for an interrupt.

Figure 10-5. Power Management Controller Block Diagram

10.5

Advanced Interrupt Controller

• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor

• Individually maskable and vectored interrupt sources

– Source 0 is reserved for the Fast Interrupt Input (FIQ)

– Source 1 is reserved for system peripherals RTT, PIT, EFC, PMC, DBGU, etc.)

– Other sources control the peripheral interrupts or external interrupts

– Programmable edge-triggered or level-sensitive internal sources

– Programmable positive/negative edge-triggered or high/low level-sensitive external

sources

• 8-level Priority Controller

– Drives the normal interrupt of the processor

– Handles priority of the interrupt sources

MCK

periph_clk[2..14]

int

UDPCK

usb_suspend

SLCK

MAINCK

PLLCK

Prescaler

/1,/2,/4,...,/64

PCK

Processor

Clock

Controller

Idle Mode

Master Clock Controller

Peripherals

Clock Controller

ON/OFF

USB Clock Controller

ON/OFF

SLCK

MAINCK

PLLCK

Prescaler

/1,/2,/4,...,/64

Programmable Clock Controller

PLLCK

Divider

/1,/2,/4

pck[0..2]

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