AT91SAM7S64 datasheet(36/42 Pages) ATMEL

36 / 42 page

6175BS–ATARM–04-Nov-05

AT91SAM7S Series Summary

Note:

1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no effect. The

System Controller is continuously clocked. The ADC clock is automatically started for the first

conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion.

11.5

Serial Peripheral Interface

• Supports communication with external serial devices

– Four chip selects with external decoder allow communication with up to 15

peripherals

– Serial memories, such as DataFlash® and 3-wire EEPROMs

– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and

Sensors

– External co-processors

• Master or slave serial peripheral bus interface

– 8- to 16-bit programmable data length per chip select

– Programmable phase and polarity per chip select

– Programmable transfer delays between consecutive transfers and between clock

and data per chip select

– Programmable delay between consecutive transfers

– Selectable mode fault detection

– Maximum frequency at up to Master Clock

Table 11-4.

Peripheral Identifiers (AT91SAM7S32)

Peripheral

Mnemonic

Peripheral

Name

External

Interrupt

AIC

Advanced Interrupt Controller

FIQ

SYSIRQ

(1)

System Interrupt

PIOA

Parallel I/O Controller A

Reserved

4ADC

(1)

Analog-to Digital Converter

SPI

Serial Peripheral Interface

USART

Reserved

SSC

Synchronous Serial Controller

TWI

Two-wire Interface

PWMC

PWM Controller

Reserved

TC0

Timer/Counter 0

TC1

Timer/Counter 1

TC2

Timer/Counter 2

15 - 29

Reserved

AIC

Advanced Interrupt Controller

IRQ0

Reserved

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