APM32F103CBT6-R datasheet(37/78 Pages) GEEHY

37 / 78 page

w w w. g e e h y. c o m

P a g e 36

Symbol

Parameter

Condition

Minimum

value

Typical

value

Maximum

value

Unit

PLS[2:0]=011 (rising edge)

2.47

2.51

2.54

PLS[2:0]=011 (falling edge)

2.37

2.40

2.46

VPVD(3)

Programmable power

supply voltage

detector voltage level

selection

PLS[2:0]=100 (rising edge)

2.57

2.60

2.63

PLS[2:0]=100 (falling edge)

2.46

2.50

2.58

PLS[2:0]=101 (rising edge)

2.66

2.71

2.74

PLS[2:0]=101 (falling edge)

2.56

2.61

2.69

PLS[2:0]=110 (rising edge)

2.77

2.81

2.86

PLS[2:0]=110 (falling edge)

2.65

2.70

2.8

PLS[2:0]=111 (rising edge)

2.86

2.91

2.92

PLS[2:0]=111 (falling edge)

2.76

2.80

2.83

VPVDhyst(2)

PVD hysteresis

107

VPOR/PDR

Power-on/power-down

reset threshold

Falling edge

1.86(1)

1.87

1.88

Rising edge

1.92

1.94

1.96

VPDRhyst (2)

PDR hysteresis

TRSTTEMPO

Reset duration

0.9

2.4

The characteristics of the product are guaranteed by design to the minimum value VPOR/PDR.

Guaranteed by design and not tested in production.

The data are obtained from a comprehensive evaluation and are not tested in production.

5.7

Power Consumption

5.7.1

Power consumption test environment

The values are measured by executing Dhrystone 2.1, with the Keil.V5 compilation environment

and the L3 compilation optimization level.

All I/O pins are in analog input mode and are connected to a static level at VDD or VSS (no load)

Unless otherwise specified, all peripherals are disabled

The relationship between Flash wait cycle setting and fHCLK:



0~24MHz: 0 wait cycle



24~48MHz: 1 wait cycle



48~72MHz: 2 wait cycles



72~96MHz: 3 wait cycles

The instruction prefetch function is enabled (note: it must be set before clock setting and bus

frequency division)

When the peripherals are enabled: fPCLK1=fHCLK/2, fPCLK2 =fHCLK

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