APM32F103CBT6-R datasheet(32/78 Pages) GEEHY

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P a g e 31

5.3.5

Static latch-up (LU)

When running a simple application (controlling the flashing of two LED through the I/O port),

the test sample is subject to false electromagnetic interference until an error is generated, and

the LED flashing indicates the generation of error. In order to evaluate the latch performance,

two complementary static latch tests need to be conducted on 6 samples:

 Provide power supply voltage exceeding the limit for each power supply pin.

 Inject current on each input, output and configurable I/O pin.

This test conforms to EIA/JESD78E integrated circuit latch standard.

Table16Static Latch-up

Symbol

Parameter

Condition

Type

Class of static

latch-up

TA=105℃, conforming to EIA/JESD78E

Class II A

Note: The samples are measured by a third-party testing organization and are not tested in production.

5.4

Memory

5.4.1

Flash characteristics

Table17 Flash Memory Characteristics

Symbol

Parameter

Condition

Minimum

value

Typical

value

Maximum

value

Unit

tprog

16-bit programming

time

TA = -40~105℃

VDD=2.4~3.6V

32.2

33.2

35.2

μs

tERASE

Page (1K bytes) erase

time

TA = -40~105℃

VDD=2.4~3.6V

1.34

1.38

1.50

tME

Mass erase time

TA = 25℃

VDD=3.3V

6.5

Vprog

Programming voltage

TA = -40~105℃

2.0

3.3

3.6

Note: The data are obtained from a comprehensive evaluation and are not tested in production.

Table18 FLASH Memory Life and Data Retention Period

Symbol

Parameter

Condition

Minimum

value

Typical

value

Maximum

value

Unit

NEND

Erasure cycles

TA =-40~85℃

100

1,000

cycles

tRET

Data retention

period

TA = 55

℃

Year

Note: The data are obtained from a comprehensive evaluation and are not tested in production.

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