APM32F103CBT6-R datasheet(19/78 Pages) GEEHY

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w w w. g e e h y. c o m

P a g e 18

Region

Start address

Peripheral name

APB2 bus

0x4001 1800

Port E

APB2 bus

0x4001 1C00

Reserved

APB2 bus

0x4001 2400

ADC1

APB2 bus

0x4001 2800

ADC2

APB2 bus

0x4001 2C00

TMR1

APB2 bus

0x4001 3000

SPI1

APB2 bus

0x4001 3400

Reserved

APB2 bus

0x4001 3800

USART1

APB2 bus

0x4001 3C00

Reserved

AHB bus

0x4002 0000

DMA

AHB bus

0x4002 0400

Reserved

AHB bus

0x4002 1000

RCM

AHB bus

0x4002 1400

Reserved

AHB bus

0x4002 2000

Flash interface

AHB bus

0x4002 2400

Reserved

AHB bus

0x4002 3000

CRC

AHB bus

0x4002 3400

Reserved

AHB bus

0xA000 0000

QSPI

—

0xA000 2000

Reserved

4.1.2

Startup configuration

At startup, the user can select one of the following three startup modes by setting the Boot pin:



Startup from main memory



Startup from system memory



Startup from built-in SRAM

Boot loader is stored in the system memory. With it, users can reprogram flash memory

through USART1.

4.2

Core

APM32F103xB core is Arm® Cortex®-M3, with working frequency of 96MHz, compatible with

mainstream Arm tools and software.

4.3

Interrupt controller

4.3.1

Nested Vector Interrupt Controller (NVIC)

It embeds a nested vector interrupt controller (NVIC) and NVIC can handle up to 49 maskable

interrupt channels (not including16 interrupt lines of Cortex®-M3) and 16 priority levels. The

interrupt vector entry address can be directly transmitted to the core, so that the interrupt

response processing with low delay can give priority to the late higher priority interrupt.

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