M50FW040 datasheet(14/41 Pages) STMICROELECTRONICS

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M50FW040

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COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations.

After power-up or a Reset operation the memory

enters Read mode.

The

commands

are

summarized

Table

7., Commands. Refer to Table 7. in conjunction

with the text descriptions below.

Read Memory Array Command. The Read Mem-

ory Array command returns the memory to its

Read mode where it behaves like a ROM or

EPROM. One Bus Write cycle is required to issue

the Read Memory Array command and return the

memory to Read mode. Once the command is is-

sued the memory remains in Read mode until an-

other command is issued. From Read mode Bus

Read operations will access the memory array.

While the Program/Erase Controller is executing a

Program or Erase operation the memory will not

accept the Read Memory Array command until the

operation completes.

Read Status Register Command. The Read Sta-

tus Register command is used to read the Status

the Read Status Register command. Once the

command is issued subsequent Bus Read opera-

tions read the Status Register until another com-

mand is issued. See the section on the Status

Read Electronic Signature Command. The Read

Electronic Signature command is used to read the

Manufacturer Code and the Device Code. One

Bus Write cycle is required to issue the Read Elec-

tronic Signature command. Once the command is

issued subsequent Bus Read operations read the

Manufacturer Code or the Device Code until an-

other command is issued.

After the Read Electronic Signature Command is

issued the Manufacturer Code and Device Code

can be read using Bus Read operations using the

addresses in Table 6.

Program Command. The

Program

command

can be used to program a value to one address in

the memory array at a time. Two Bus Write opera-

tions are required to issue the command; the sec-

ond Bus Write cycle latches the address and data

in the internal state machine and starts the Pro-

gram/Erase Controller. Once the command is is-

sued subsequent Bus Read operations read the

Status Register. See the section on the Status

If the address falls in a protected block then the

Program operation will abort, the data in the mem-

ory array will not be changed and the Status Reg-

ister will output the error.

During the Program operation the memory will

only accept the Read Status Register command

and the Program/Erase Suspend command. All

other commands will be ignored. Typical Program

times are given in Table 12.

Note that the Program command cannot change a

bit set at ‘0’ back to ‘1’ and attempting to do so will

not cause any modification on its value. The Erase

command must be used to set all of the bits in the

block to ‘1’.

See Figure 19., Program Flowchart and Pseudo

Code, for a suggested flowchart on using the Pro-

gram command.

Erase Command. The Erase command can be

used to erase a block. Two Bus Write operations

are required to issue the command; the second

Bus Write cycle latches the block address in the in-

ternal state machine and starts the Program/Erase

Controller. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister. See the section on the Status Register for

details on the definitions of the Status Register

bits.

If the block is protected then the Erase operation

will abort, the data in the block will not be changed

and the Status Register will output the error.

During the Erase operation the memory will only

accept the Read Status Register command and

the Program/Erase Suspend command. All other

commands will be ignored. Typical Erase times

are given in Table 12.

The Erase command sets all of the bits in the block

to ‘1’. All previous data in the block is lost.

See Figure 21., Erase Flowchart and Pseudo

Code, for a suggested flowchart on using the

Erase command.

Clear Status Register Command. The Clear Sta-

tus Register command can be used to reset bits 1,

3, 4 and 5 in the Status Register to ‘0’. One Bus

Write is required to issue the Clear Status Register

command. Once the command is issued the mem-

ory returns to its previous mode, subsequent Bus

Read operations continue to output the same data.

The bits in the Status Register are sticky and do

not automatically return to ‘0’ when a new Program

or Erase command is issued. If an error occurs

then it is essential to clear any error bits in the Sta-

tus Register by issuing the Clear Status Register

command before attempting a new Program or

Erase command.

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