M50FW040 datasheet(12/41 Pages) STMICROELECTRONICS

12 / 41 page

M50FW040

12/41

subset of the features available to the Firmware

Hub (FWH) Interface are available; these include

all the Commands but exclude the Security fea-

tures and other registers.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux)

Interface is selected all the blocks are unprotect-

ed. It is not possible to protect any blocks through

this interface.

Bus Read. Bus Read operations are used to out-

put the contents of the Memory Array, the Elec-

tronic Signature and the Status Register. A valid

Bus Read operation begins by latching the Row

Address and Column Address signals into the

memory using the Address Inputs, A0-A10, and

the Row/Column Address Select RC. Then Write

Enable (W) and Interface Reset (RP) must be

High, VIH, and Output Enable, G, Low, VIL, in order

to perform a Bus Read operation. The Data Inputs/

Outputs will output the value, see Figure 14., A/A

Mux Interface Read AC Waveforms, and Table

22., A/A Mux Interface Read AC Characteristics,

for details of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by latching the Row Address and Column

Address signals into the memory using the Ad-

dress Inputs, A0-A10, and the Row/Column Ad-

dress Select RC. The data should be set up on the

Data Inputs/Outputs; Output Enable, G, and Inter-

face Reset, RP, must be High, VIH and Write En-

able, W, must be Low, VIL. The Data Inputs/

Outputs are latched on the rising edge of Write En-

able, W. See Figure 15., A/A Mux Interface Write

AC Waveforms, and Table 23., A/A Mux Interface

Write AC Characteristics, for details of the timing

requirements.

Output Disable. The data outputs are high-im-

pedance when the Output Enable, G, is at VIH.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when RP is Low, VIL. RP must be

held Low, VIL for tPLPH. If RP is goes Low, VIL, dur-

ing a Program or Erase operation, the operation is

aborted and the memory cells affected no longer

contain valid data; the memory can take up to tPL-

RH to abort a Program or Erase operation.

Table 4. FWH Bus Read Field Definitions

Clock

Cycle

Number

Clock

Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

Description

START

1101b

On the rising edge of CLK with FWH4 Low, the contents of FWH0-

FWH3 indicate the start of a FWH Read cycle.

IDSEL

XXXX

Indicates which FWH Flash Memory is selected. The value on FWH0-

FWH3 is compared to the IDSEL strapping on the FWH Flash

Memory pins to select which FWH Flash Memory is being addressed.

3-9

ADDR

XXXX

A 28-bit address phase is transferred starting with the most significant

nibble first.

MSIZE

0000b

Always 0000b (only single byte transfers are supported).

TAR

1111b

The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

TAR

1111b

(float)

The FWH Flash Memory takes control of FWH0-FWH3 during this

cycle.

13-14

WSYNC

0101b

The FWH Flash Memory drives FWH0-FWH3 to 0101b (short wait-

sync) for two clock cycles, indicating that the data is not yet available.

Two wait-states are always included.

RSYNC

0000b

The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating

that data will be available during the next clock cycle.

16-17

DATA

XXXX

Data transfer is two CLK cycles, starting with the least significant

nibble.

TAR

1111b

The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a

turnaround cycle.

TAR

1111b

(float)

N/A

The FWH Flash Memory floats its outputs, the host takes control of

FWH0-FWH3.

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