TMS320VC549 datasheet(26/64 Pages) TI

номер детали	TMS320VC549

подробное описание детали	FIXED-POINT DIGITAL SIGNAL PROCESSOR

PDF	64 Pages

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производитель	TI [Texas Instruments]

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TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078G − SEPTEMBER 1998 − REVISED OCTOBER 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

memory and parallel I/O interface timing (continued)

timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 7)

549-80

549-100

549-120

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

ta(A)IO

Access time, read data access from address valid

3H−9

3H−8

ta(ISTRBL)IO

Access time, read data access from IOSTRB low

2H−9

2H−8

2H−7

tsu(D)IOR

Setup time, read data before CLKOUT high

th(D)IOR

Hold time, read data after CLKOUT high

th(ISTRBH-D)R

Hold time, read data after IOSTRB high

† Address and IS timings are included in timings referenced as address.

‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.

R/W

IOSTRB

D[15:0]

A[15:0]

CLKOUT

th(A)IOR

td(CLKH-ISTRBH)

th(D)IOR

tsu(D)IOR

ta(A)IO

td(CLKH-ISTRBL)

td(CLKL-A)

ta(ISTRBL)IO

th(ISTRBH-D)R

Figure 7. Parallel I/O Port Read (IOSTRB = 0)

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