MAXQ3180-RAN+ datasheet(34/48 Pages) MAXIM

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Note that analog scan slot 7 is reserved for temperature

measurements. There is no need to explicitly enable

this measurement slot, since it is automatically activat-

ed when either the TMPC0 (single temperature mea-

surement command) or TMPC1 (double temperature

measurement command) bits are set by the master.

The required time for a each analog scan slot measure-

ment (tC) is determined by the MAXQ3180 system

clock frequency, the setting of the ADC clock division

bits (ADCCD0 and ADCCD1) in the R_ACFG hardware

Using the default register settings (ADCCD[1:0] = 00b

and ADCRATE = C7h = 199d), the time for each analog

slot measurement (tC) is 25μs when the MAXQ3180 is

running at 8MHz. Since there are eight analog scan

slots in the measurement frame, the total time for all

measurements (tF) is tC x 8. Using the default settings

with the MAXQ3180 running at 8MHz, the entire

sequence of measurements takes 200μs to complete,

which, in turn, means that 200μs will elapse, for exam-

ple, between one phase A current measurement and

the next.

Even if some of the analog measurement slots (such as

neutral current or temperature measurement) are

skipped by setting the NOCONV bit in that slot’s

SCAN_x register to 1, the time period for that slot will

remain in the frame, ensuring that the total frame time is

always tC x 8, regardless of which individual slots are

enabled or disabled.

Digital Processing

As voltage and current samples are collected, the

MAXQ3180 performs a variety of digital filtering, accu-

mulation, and processing calculations to arrive at

meter-reading values (such as line frequency, RMS

voltage and current, and active and reactive power)

that can then be read by the master. The MAXQ3810

calculates and detects values and conditions including

the following:

• Zero-crossing detection

• Line frequency and line period calculation

• RMS voltage (phase A, phase B, phase C)

• RMS current (phase A, phase B, phase C, neutral

current)

• Power (active, reactive, and apparent) for each

phase

• Energy accumulation (including energy pulse output

function)

• Peak voltage (phase A, phase B, phase C)

• Peak current (phase A, phase B, phase C)

• Voltage sag condition

• Tamper condition detection

Voltage Zero-Crossing Detection

The MAXQ3180 monitors each of the three voltage

input signals (from phase A, phase B, and phase C)

and detects zero-crossing events on each of them indi-

vidually. The sequence of the detected zero crossings

and the intervals between them are then used to calcu-

late additional data.

Before zero-crossing detection is performed, each of

the three voltage inputs (VA, VB, and VC) are passed

through a first-order lowpass filter (LPF) with a cutoff

frequency near 50Hz to reduce harmonics, which can

trigger false zero-crossing events. The master can con-

figure this LPF by setting the register LPF_B0FZC. The

equation for the zero-crossing LPF (for all three voltage

phase inputs) is as follows:

Yn = Yp + (Xn - Yp) x LPF_B0FZC/216

Although the filtered waveform output is not a perfect

sine wave, the LPF ensures that the output has no more

than one ascending zero crossing per line period.

Following the LPF filter processing stage, the

MAXQ3180 scans the voltage signals to detect ascend-

ing zero-crossing events for each voltage phase.

Line Frequency and Period Measurement

For each phase A, B, and C, the MAXQ3180 counts the

number of scan frames (NS) between two consecutive

zero crossings. The NS is a global value, common for

all three phases, and is located in RAM at address

0x08C. Each individual phase A, B, or C zero-crossing

event contributes raw NS count, which plugs as input to

the LPF.

Low-Power, Multifunction, Polyphase AFE

______________________________________________________________________________________

Table 7. Analog Scan Slot Time Selection

ADCCD1

ADCCD0

ADC CLOCK DIVISION RATE

ANALOG SCAN SLOT TIME (tC)

Divide by 1 (default)

1/fCLK x (R_ADCRATE[8:0] + 1)

Divide by 2

2/fCLK x (R_ADCRATE[8:0] + 1)

Divide by 4

4/fCLK x (R_ADCRATE[8:0] + 1)

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