43
0832F–HIREL–02/07
e2v semiconductors SAS 2007
PC7410
The PC7410 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock
frequency of the PC7410. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop
(DLL) circuit and should be routed from the PC74107410 to the external RAMs. A separate clock output,
L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on
pin L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the
clocking of the internal latches in the L2 bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register.
Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the
frequency of the PC7410 core, and the phase adjustment range that the L2 DLL supports. Table 13-2
shows various example L2 clock frequencies that can be obtained for a given set of core frequencies.
The minimum L2 frequency target is 133 MHz. Sample core-to-L2 frequencies for the PC7410 is shown
in Table 13-2. In this example, shaded cells represent settings that, for a given core frequency, result in
L2 frequencies that do not comply with the minimum and maximum L2 frequencies listed in Table 9-6 on
page 28.
Note:
The core and L2 frequencies are for reference only. Some examples may represent core or L2 frequencies
which are not useful, not supported or not tested for by the PC7410; see “L2 Clock AC Specifications” on
page 24 for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less than
150 MHz.
14. System Design Information
14.1
PLL and DLL Power Supply Filtering
The AV
DD and L2AVDD power signals are provided on the PC7410 to supply power to the PLL and DLL,
respectively. Both AV
DD and L2AVDD can be supplied power from the VDD power plane. High frequency
noise in the 500 kHz to 10 MHz resonant frequency range of the PLL on the V
DD power plane could
affect the stability of the internal clocks.
On systems that use the PC7410 HCTE device, the AV
DD and L2AVDD input signals should both imple-
ment the circuit shown in Figure 14-1 on page 44.
On systems that use the PC7410 CBGA device, the L2AV
DD input should implement the circuit shown in
Figure 14-1.
Table 13-2.
Sample Core-to-L2 Frequencies
Core Frequency in MHz
÷1
÷1.5
÷2
÷2.5
÷3
÷3.5
÷4
350
350
233
175
140
–
–
–
366
366
244
183
147
–
–
–
400
400
266
200
160
133
–
–
433
–
288
216
173
144
–
–
450
–
300
225
180
150
–
–
466
–
311
233
186
155
133
–
500
–
333
250
200
166
143
–
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