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0832F–HIREL–02/07
PC7410
e2v semiconductors SAS 2007
Figure 9-7.
L2 Bus Output Timing Diagram
Note:
VM = Midpoint Voltage (L2OVDD/2)
Figure 9-8.
AC Test Load for the L2 Interface
9.2.5
IEEE 1149.1 AC Timing Specifications
Table 9-6 provides the IEEE
® 1149.1 (JTAG) AC timing specifications as defined in Figure 9-9 on page
29, Figure 9-10 on page 29, Figure 9-11 on page 29 and Figure 9-12 on page 30.
L2SYNC_IN
All Outputs
tL2CHOV
tL2CHOX
VM
VM
tL2CHOZ
L2DATA BUS
Z0 = 50
Ω
RL = 50
Ω
L2OVDD/2
Output
Table 9-6.
JTAG AC Timing Specifications (Independent of SYSCLK) (1)at Recommended Operating
Conditions (see Table 6-3 on page 11)
Symbol
Parameter
Min
Max
Unit
fTCLK
TCK frequency of operation
0
33.3
MHz
t
TCLK
TCK cycle time
30
ns
t
JHJL
TCK clock pulse width measured at OV
DD/2
15
ns
tJR & tJF
TCK rise and fall times
0
2
ns
t
TRST
(2)
TRST assert time
25
ns
t
DVJH
(3)
tIVJH
Input Setup Times:
Boundary-scan data
TMS, TDI
4
0
ns
tDXJH
(3)
t
IXJH
Input Hold Times:
Boundary-scan data
TMS, TDI
20
25
ns
t
JLDV
(4)
t
JLOV
Valid Times:
Boundary-scan data
TDO
4
4
20
25
ns
t
JLDZ
(4)(5)
tJLOZ
(5)
TCK to output high impedance:
Boundary-scan data
TDO
3
3
19
9
ns
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