20
0832F–HIREL–02/07
PC7410
e2v semiconductors SAS 2007
8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see VIL/VIH/VOL/VOH/CVIH/CVIL DC limits of 1.8V mode
while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by the UpdateIR TAP state
until a different instruction is loaded into the instruction register by either another UpdateIR or a Test-Logic-Reset TAP state.
If only TSRT is asserted to the part, and then a SAMPLE instruction is executed, there is no way to control or predict what
the DC voltage limits are. If HRESET is asserted before executing a SAMPLE instruction, the DC voltage limits will be con-
trolled by the BVSEL/L2VSEL settings during HRESET. Anytime HRESET is not asserted (i.e., just asserting TRST), the
voltage mode is not known until either EXTEST or CLAMP is executed, at which time the voltage level will be at the DC limits
of 1.8V.
9.2
Dynamic Characteristics
After fabrication, parts are sorted by maximum processor core frequency as shown in “Clock AC Specifi-
cations” and tested for conformance to the AC specifications for that frequency. These specifications are
for valid processor core frequencies. The processor core frequency is determined by the bus (SYSCLK)
frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum processor core
frequency.
9.2.1
Clock AC Specifications
Table 9-2 provides the clock AC timing specifications as defined in Figure 9-1 on page 21.
Note:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) fre-
quency, CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:3] signal description in “Clock Selection” on page 42 for valid PLL_CFG[0:3] settings.
2. Rise and fall times for the SYSCLK input measured from 0.4V to 2.4V when OV
DD = 3.3V nominal.
3. Rise and fall times for the SYSCLK input measured from 0.2V to 1.2V when OVDD = 1.8V or 2.5V nominal.
4. Timing is guaranteed by design and characterization.
5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.
6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for
PLL lock after a stable V
DD and SYSCLK are reached during the power-on reset sequence. This specification also applies
when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Table 9-2.
Clock AC Timing Specifications (See Table 6-3 on page 11 for Recommended Operating Conditions)
Symbol
Characteristic
Maximum Processor Core Frequency
Unit
400 MHz
450 MHz
500 MHz
Min
Max
Min
Max
Min
Max
fCORE
(1)
Processor frequency
350
400
350
450
350
500
MHz
f
VCO
(1)
VCO frequency
700
800
700
900
700
1000
MHz
fSYSCLK
(1)
SYSCLK frequency
33
133
33
133
33
133
MHz
t
SYSCLK
SYSCLK cycle time
7.5
30
7.5
30
7.5
30
ns
t
KR & tKF
(2)
SYSCLK rise and fall time
1.0
1.0
1
ns
tKR & tKF
(3)
0.5
0.5
0.5
ns
t
KHKL/tSYSCLK
(4)
SYSCLK duty cycle measured at OV
DD/2
40
60
40
60
40
60
%
SYSCLK jitter(5)
±150
±150
±150
ps
Internal PLL relock time(6)
100
100
100
µs
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