AX99100QI datasheet(4/70 Pages) ASIX

4 / 70 page

AX99100

PCIe to Multi I/O Controller

Table of Contents

INTRODUCTION......................................................................................................................................... 6

GENERAL DESCRIPTION ........................................................................................................................... 6

1.1

AX99100 BLOCK DIAGRAM .................................................................................................................... 7

1.2

AX99100 PINOUT DIAGRAM ................................................................................................................... 8

1.3

SIGNAL DESCRIPTION .............................................................................................................................. 9

1.4

1.4.1

GPIO and Mode Setting ................................................................................................................ 11

1.4.2

Serial Interface for COM Port ...................................................................................................... 12

1.4.3

Serial Interface for Multi-Protocol Transceiver ........................................................................... 13

1.4.4

Serial Port with GPIO enabled ..................................................................................................... 14

1.4.5

Serial Port with Function Disabled............................................................................................... 15

1.4.6

Parallel Port.................................................................................................................................. 16

1.4.7

SPI Interface.................................................................................................................................. 17

1.4.8

Local Bus Interface ....................................................................................................................... 18

FUNCTION DESCRIPTION..................................................................................................................... 19

CLOCKS/RESETS AND POWER ................................................................................................................ 19

2.1

PCIE OPERATION ................................................................................................................................... 19

2.2

2C CONTROLLER ................................................................................................................................... 21

2.3

SERIAL PORT (SP).................................................................................................................................. 21

2.4

PARALLEL PORT (PP)............................................................................................................................. 21

2.5

SPI MASTER CONTROLLER (SPI) ........................................................................................................... 22

2.6

LOCAL BUS CONTROLLER (LB) ............................................................................................................. 23

2.7

GPIO FUNCTION .................................................................................................................................... 24

2.8

POWER MANAGEMENT........................................................................................................................... 24

2.9

CHIP CONFIGURATION ......................................................................................................................... 25

BOOT STRAPPING PINS FOR CHIP MODE ................................................................................................ 25

3.1

DTR BOOT STRAPPING PINS FOR SERIAL PORT ..................................................................................... 26

3.2

HARDWARE CONFIGURATION EEPROM ............................................................................................... 27

3.3

3.3.1

Configuration EEPROM Memory Map for None Local Bus Interface ......................................... 28

3.3.2

Configuration EEPROM Memory Map for Local Bus Interface ................................................... 34

3.3.3

Hardware Default Values Summary.............................................................................................. 43

3.3.4

Disable Unused PCIe Function in HWCFGEE............................................................................. 46

PCIE CONFIGURATION SPACE MAP........................................................................................................ 49

3.4

ELECTRICAL SPECIFICATIONS ......................................................................................................... 51

DC CHARACTERISTICS........................................................................................................................... 51

4.1

4.1.1

Absolute Maximum Ratings........................................................................................................... 51

4.1.2

Recommended Operating Condition ............................................................................................. 51

4.1.3

Leakage Current and Capacitance................................................................................................ 51

4.1.4

DC Characteristics of 3.3V with 5V Tolerant I/O Pins ................................................................. 52

4.1.5

DC Characteristics of Voltage Regulator ..................................................................................... 52

PCIE SPECIFICATIONS ............................................................................................................................ 53

4.2

POWER CONSUMPTION........................................................................................................................... 54

4.3

POWER–UP/DOWN AND POWER MANAGEMENT SEQUENCE.................................................................... 55

4.4

AC TIMING CHARACTERISTICS .............................................................................................................. 56

4.5

4.5.1

PCIe Reference Clock Timing ....................................................................................................... 56

4.5.2

2C Timing ..................................................................................................................................... 56

4.5.3

Serial Port Timing......................................................................................................................... 57

4.5.4

SPI Timing..................................................................................................................................... 58

4.5.5

Local Bus Timing .......................................................................................................................... 59

PACKAGE INFORMATION .................................................................................................................... 68

ORDERING INFORMATION .................................................................................................................. 69

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