AX99100QI datasheet(29/70 Pages) ASIX

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AX99100

PCIe to Multi I/O Controller

Divide Clock Selection (0x00)

Bit

Description

1:0

Clock source select for LB or SPI used.

00: 125MHz from internal PLL.

01: 100MHz from PCIe reference clock.

1x: EXT_CLK.

Hardware Default Value:

01: In LB and SPI mode.

00: Others.

Divide Enable.

0: Disabled clock divider to LB and SPI module.

1: Enabled clock divider to generate desired clock frequency for LB or SPI module.

Hardware Default Value:

1: In LB and SPI mode.

0: Others.

7:3

Reserved

Note: “ Hardware Default Value” means HWCFGEE load failed for without Hardware Configuration EEPROM

or checksum failed.

Divide Register (0x01)

Bit

Description

7:0

Clock Divider N Register.

The number of N in this field is used to generate the desired clock frequency and the frequency will

follow following equation:

Desired clock frequency = (125MHz or 100MHz or EXT_CLK) / N

Note:

◎ N equal to 0x00 or 0x01 is divided by 1, N = ‘2’ is divided by 2, and so on.

◎ This value N should >= 2 when the clock source from 125MHz and 100MHz for SPI.

Hardware Default Value:

0x02: In LB and SPI mode.

0x00: Others.

Vendor ID_Fx (0x03~0x02, 0x18~0x17, 0x2C~0x2B, 0x40~0x3F)

Bit

Description

15:0

Vendor ID_Fx.

This field will be loaded into PCIe Configuration Space offset 0x00 (Vendor ID).

Hardware Default Value: 0x125B.

Note 1: Vendor ID_F3 = 0xFFFF In PP mode, Vendor ID_F2 = 0xFFFF In SPI mode.

Note 2: Only “Vendor ID_F0” existed in LB mode.

Note: “ x” is from 0~3 means PCIe function 0~3.

Device ID_Fx (0x05~0x04, 0x1A~0x19, 0x2E~0x2D, 0x42~0x41)

Bit

Description

15:0

Device ID_Fx.

This field will be loaded into PCIe Configuration Space offset 0x02 (Device ID).

Hardware Default Value: 0x9100

Note 1: Device ID_F3 = 0xFFFF In PP mode, Device ID_F2 = 0xFFFF In SPI mode.

Note 2: Only “Device ID_F0”=(0x9110) existed in LB mode.

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