AX99100QI datasheet(18/70 Pages) ASIX

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AX99100

PCIe to Multi I/O Controller

1.4.8

Local Bus Interface

Table 1-11: Local Bus Pin Description

Local Bus Interface

Pin Name

Type

Pin No

Pin Description

A0/ CHIP_MODE[2]

O5/4m

Local Bus Address Bus, A[2:0]

These pins are input direction during chip reset use to bootstrap the mode setting

to decide the operation mode. Please reference to Section 3.1.

In Local Bus mode, These pins should always use external pull-down resistors to

ground.

A1/ CHIP_MODE[1]

O5/4m

A2/ CHIP_MODE[0]

O5/4m

Local Bus Address Bus, A[3]

This pin should be connected to the 3.3V AUX in PCIe slot via an external

pull-up resistor. It is used to detect the 3.3V AUX is existed or not.

A[9:4]

O5/4m

60, 59,

47, 48,

49, 50

Local Bus Address Bus, A[9:4]

The A[9:0] are outputs and provide up to 10 Local Bus address lines in

non-multiplexed address and data bus format

AD[15:0]

B5/4m

61, 62,

63, 64,

65, 66,

67, 68,

1, 2,

4, 3,

5, 7,

8, 9

Data and Address bus

Multiplexed mode: address on bus when ALE issued, other time data on bus

Non-multiplexed mode: data always on bus

RSTO

B5/4m

Local Bus Reset Output

The output polarity can be decided by adding external pull up/down resistor. If

connected this pin to VCCIO via external pull-up resistor, means RSTO is active

high. If pull-down to ground, means active low.

CLKO

B5/8m

Local Bus Clock Output

CS1n

CS0n

O5/4m

Local Bus Chip Select 1

Local Bus Chip Select 0

DREQ[1:0]

44, 46

DMA Request

DACK[1:0]

O5/4m

43, 45

DMA Acknowledge

INT[1:0]

31, 32

Interrupt

ALE

O5/4m

Address Latch Enable

When in non-multiplexed mode, ALE can choice remap to A[10] (detail

description same as above A[9:0]) or address latch enable for ISA bus type

When in multiplexed mode, ALE for address latch enable

RDn

O5/4m

Local Bus Read Cycle

WRn

O5/4m

Local Bus Write Cycle

RDY

Local Bus Device Ready

Note: Above signals are only valid when CHIP_MODE = 000.

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