AX99100QI datasheet(22/70 Pages) ASIX

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AX99100

PCIe to Multi I/O Controller

SPI Master Controller (SPI)

2.6

The AX99100 contain the High Speed Serial Peripheral Interface (SPI) Master Controller provides a full-duplex,

synchronous serial communication interface (4 wires) to flexibly work with numerous SPI peripheral devices. The

High Speed SPI Controller consists of a High Speed SPI master controller with 3 slave select pins, SS[2:0], to connect

up to 7 SPI devices.

This High Speed SPI master controller supports 4 types of interface timing mode, namely, Mode 0, Mode 1, Mode 2,

and Mode 3 to allow working with most SPI devices available. It supports MSB/LSB first data transfer. The SCLK

SPI clock is programmable by software and can run up to 42MHz. The AX99100 also provides many programmable

registers can be used to adjust the bus timing to fit the variety Slave timing requirements. Please reference the section

4.5.4.

The AX99100 SPI master supports four kinds of access types below.

Non-Burst-Type Transfer: Supports up to 8 bytes registers can be read and written by Software with none DMA

access.

Burst-Type Transfer: Supports TX/RX DMA transfer. Upon configured by software and one DMA length up to

64K bytes, SPI RX DMA supports moving data from SPI bus through SPI RX FIFO into PCIe BUS; SPI TX DMA

supports moving data from PCIe BUS through SPI TX FIFO to SPI bus.

Burst-Type with OP-code Transfer: supports up to 8 bytes pre-programmable OP code automatic insertion in each

Burst-Type Transfer with successive chip select assertion, to reduce CPU/software loading.

Fragmentation: supports to fragment large data block into several smaller transfers on SPI bus with programmable

length for each small transfer fragment, to reduce CPU/software loading.

AX99100QI датащи(PDF) 22 Page - ASIX Electronics Corporation