7.2.3 Application Curves

Time ( 10 ) (s)

X

–9

0.0

–0.5

0.5

–0.4

0.4

–0.3

0.3

–0.2

0.2

–0.1

0.1

0.0

0.2

0.4

0.5

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Figure 7-2. Eye Pattern: 480-Mbps USB Signal With

No Switch (Through Path)

Time ( 10 ) (s)

X

–9

0.0

–0.5

0.5

–0.4

0.4

–0.3

0.3

–0.2

0.2

–0.1

0.1

0.0

0.2

0.4

0.5

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Figure 7-3. Eye Pattern: 480-Mbps USB Signal With

Switch 1D Path

Time ( 10 ) (s)

X

–9

0.0

–0.5

0.5

–0.4

0.4

–0.3

0.3

–0.2

0.2

–0.1

0.1

0.0

0.2

0.4

0.5

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Figure 7-4. Eye Pattern: 480-Mbps USB Signal With Switch 2D Path

7.3 Power Supply Recommendations

Make sure that the power to the device supplied through the VCC pin follows the USB 1.0, 1.1, and 2.0

standards. TI recommends placing a bypass capacitor as close as possible to the supply pin VCC to help smooth

out lower frequency noise to provide better load regulation across the frequency spectrum.

7.4 Layout

7.4.1 Layout Guidelines

Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the

D+/D– traces.

The high speed D+/D– traces should always be matched lengths and must be no more than 4 inches; otherwise,

the eye diagram performance can be degraded. A high-speed USB connection is made through a shielded,

twisted pair cable with a differential characteristic impedance. In layout, the impedance of D+ and D– traces

should match the cable characteristic differential impedance for optimal performance.

Route the high-speed USB signals using a minimum of vias and corners to reduce signal reflections and

impedance changes. When a via must be used, increase the clearance size around the via to minimize the

capacitance. Each via introduces discontinuities in the transmission line of the signal and increases the chance

of picking up interference from the other layers of the board. Be careful when designing test points on twisted

pair lines; through-hole pins are not recommended.

When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This

reduces reflections on the signal traces by minimizing impedance discontinuities.

Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,

mounting holes, magnetic devices or ICs that use or duplicate clock signals.

TS3USB221E

SCDS263E – SEPTEMBER 2009 – REVISED JULY 2024

www.ti.com

14

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