TMS320VC5507 datasheet(13/142 Pages) TI2

13 / 142 page

Features

April 2004 − Revised January 2008

SPRS244J

TMS320VC5507 Features

D High-Performance, Low-Power, Fixed-Point

TMS320C55x

 Digital Signal Processor

− 9.26-, 6.95-, 5-ns Instruction Cycle Time

− 108-, 144-, 200-MHz Clock Rate

− One/Two Instruction(s) Executed per

Cycle

− Dual Multipliers [Up to 400 Million

Multiply-Accumulates per Second

(MMACS)]

− Two Arithmetic/Logic Units (ALUs)

− Three Internal Data/Operand Read Buses

and Two Internal Data/Operand Write

Buses

D 64K x 16-Bit On-Chip RAM, Composed of:

− 64K Bytes of Dual-Access RAM (DARAM)

8 Blocks of 4K

× 16-Bit

− 64K Bytes of Single-Access RAM

(SARAM) 8 Blocks of 4K

× 16-Bit

D 64K Bytes of One-Wait-State On-Chip ROM

(32K

× 16-Bit)

D 8M × 16-Bit Maximum Addressable External

Memory Space (Synchronous DRAM)

D 16-Bit External Parallel Bus Memory

Supporting Either:

− External Memory Interface (EMIF) With

GPIO Capabilities and Glueless Interface

to:

− Asynchronous Static RAM (SRAM)

− Asynchronous EPROM

− Synchronous DRAM (SDRAM)

− 16-Bit Parallel Enhanced Host-Port

Interface (EHPI) With GPIO Capabilities

D Programmable Low-Power Control of Six

Device Functional Domains

D On-Chip Scan-Based Emulation Logic

D On-Chip Peripherals

− Two 20-Bit Timers

− Watchdog Timer

− Six-Channel Direct Memory Access

(DMA) Controller

− Three Multichannel Buffered Serial Ports

(McBSPs)

− Programmable Phase-Locked Loop

Clock Generator

− Seven (LQFP) or Eight (BGA) General-

Purpose I/O (GPIO) Pins and a General-

Purpose Output Pin (XF)

− USB Full-Speed (12 Mbps) Slave Port

Supporting Bulk, Interrupt and

Isochronous Transfers

− Inter-Integrated Circuit (I2C) Multi-Master

and Slave Interface

− Real-Time Clock (RTC) With Crystal

Input, Separate Clock Domain, Separate

Power Supply

− 4-Channel (BGA) or 2-Channel (LQFP)

10-Bit Successive Approximation A/D

D IEEE Std 1149.1† (JTAG) Boundary Scan

Logic

D Packages:

− 144-Terminal Low-Profile Quad Flatpack

(LQFP) (PGE Suffix)

− 179-Terminal MicroStar BGA

 (Ball Grid

Array) (GHH and ZHH Suffixes)

D 1.2-V Core (108 MHz), 2.7-V – 3.6-V I/Os

D 1.35-V Core (144 MHz), 2.7-V – 3.6-V I/Os

D 1.6-V Core (200 MHz), 2.7-V – 3.6-V I/Os

All trademarks are the property of their respective owners.

TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.

† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

TMS320VC5507 датащи(PDF) 13 Page - Texas Instruments

TMS320VC5507 датащи(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL