TMS320VC5507 datasheet(49/142 Pages) TI2

49 / 142 page

Functional Overview

April 2004 − Revised January 2008

SPRS244J

3.7

System Register

The system register (SYSR) provides control over certain device-specific functions. The register is located

at port address 07FDh.

Reserved

CLKDIV

R/W

LEGEND: R = Read, W = Write, n = value after reset

Figure 3−16. System Register Bit Locations

Table 3−15. System Register Bit Fields

BIT

FUNCTION

NUMBER

NAME

FUNCTION

15−3

Reserved

These bits are reserved and are unaffected by writes.

2−0

CLKDIV

CLKOUT Divide Factor. Allows the clock present on the CLKOUT pin to be a divided-down version

of the internal CPU clock. This field does not affect the programming of the PLL.

CLKDIV 000 = CLKOUT represents the CPU clock divided by 1

CLKDIV 001 = CLKOUT represents the CPU clock divided by 2

CLKDIV 010 = CLKOUT represents the CPU clock divided by 4

CLKDIV 011 = CLKOUT represents the CPU clock divided by 6

CLKDIV 100 = CLKOUT represents the CPU clock divided by 8

CLKDIV 101 = CLKOUT represents the CPU clock divided by 10

CLKDIV 110 = CLKOUT represents the CPU clock divided by 12

CLKDIV 111 = CLKOUT represents the CPU clock divided by 14

3.8

USB Clock Generation

The USB module can be clocked from either an Analog Phase-Locked Loop (APLL) or a Digital Phase-Locked

Loop (DPLL). The APLL is the recommended USB clock source due to better noise tolerance and less

long-term jitter than the DPLL. To maintain the backward compatibility, the DPLL is the power-up default clock

source for the USB module.

USB

APLL

DPLL

USB

USB Module Clock

(48.0 MHz)

PLLSEL

CLKIN

Figure 3−17. USB Clock Generation

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