TMS320VC5507 datasheet(44/142 Pages) TI2

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Functional Overview

April 2004 − Revised January 2008

SPRS244J

3.6

General-Purpose Input/Output (GPIO) Ports

3.6.1 Dedicated General-Purpose I/O

The 5507 provides eight dedicated general-purpose input/output pins, GPIO0−GPIO7. Each pin can be

indepedently configured as an input or an output using the I/O Direction Register (IODIR). The I/O Data

of pins configured as outputs. See Table 3−29 for address information. The description of the IODIR is shown

in Figure 3−8 and Table 3−7. The description of IODATA is shown in Figure 3−9 and Table 3−8.

To configure a GPIO pin as an input, clear the direction bit that corresponds to the pin in IODIR to 0. To read

the logic state of the input pin, read the corresponding bit in IODATA.

To configure a GPIO pin as an output, set the direction bit that corresponds to the pin in IODIR to 1. To control

the logic state of the output pin, write to the corresponding bit in IODATA.

Reserved

IO7DIR

IO6DIR

IO5DIR

(BGA)

IO4DIR

IO3DIR

IO2DIR

IO1DIR

IO0DIR

R−00000000

R/W−0

LEGEND: R = Read, W = Write, n = value after reset

Figure 3−8. I/O Direction Register (IODIR) Bit Layout

Table 3−7. I/O Direction Register (IODIR) Bit Functions

BIT

NO.

BIT

NAME

RESET

VALUE

FUNCTION

15−8

Reserved

These bits are reserved and are unaffected by writes.

7−0

IOxDIR†

IOx Direction Control Bit. Controls whether IOx operates as an input or an output.

IOxDIR = 0

IOx is configured as an input.

IOxDIR = 1

IOx is configured as an output.

† The GPIO5 pin is available on the BGA package only.

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