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TMS320VC33 датащи(PDF) 44 Page - Texas Instruments

номер детали TMS320VC33
подробное описание детали  DIGITAL SIGNAL PROCESSOR
PDF  59 Pages
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TMS320VC33 датащи(HTML) 44 Page - Texas Instruments

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TMS320VC33
DIGITAL SIGNAL PROCESSOR
SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal.
NOTE: The IACK instruction can be executed at anytime to signal an event using the IACK pin. The IACK
instruction is most often used within an interrupt routine to signal which interrupt has occurred. The IACK
instruction must be executed to generate the IACK pulse.
switching characteristics over recommended operating conditions for IACK (see Figure 30)
PARAMETER
VC33-120
VC33-150
UNIT
PARAMETER
MIN MAX
MIN MAX
UNIT
td(H1H-IACKL)
Delay time, H1 high to IACK low
--1
4
--1
3
ns
td(H1H-IACKH)
Delay time, H1 high to IACK high
--1
4
--1
3
ns
H3
H1
IACK
ADDR
Data
Fetch IACK
Instruction
IACK Data
Read
Decode IACK
Instruction
td(H1H-IACKL)
td(H1H-IACKH)
Figure 30. Interrupt Acknowledge (IACK) Timing



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