TMS320VC33 datasheet(26/59 Pages) TI2

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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)†

PARAMETER

TEST CONDITIONS‡

MIN

TYP§

MAX

UNIT

VOH

High-level output voltage

DVDD =MIN, IOH =MAX

2.4

VOL

Low-level output voltage

DVDD =MIN, IOL =MAX

0.4

High-impedance current

DVDD =MAX

-- 5

μA

Input current

VI =VSS to DVDD

-- 5

μA

IIPU

Input current (with internal pullup)

Inputs with internal pullups¶

-- 600

μA

IIPD

Input current (with internal pulldown)

Inputs with internal pulldowns¶

600

-- 10

μA

IBKU

Input current (with bus keeper) pullup#

Bus keeper opposes until conditions match

-- 600

μA

IBKD

Input current (with bus keeper) pulldown#

600

-- 10

μA

Supply current pins||k

TC =25°C,

fx =60MHz

VC33-120

120

IDDD

Supply current, pins||k

TC = 25 C,

DVDD =MAX

fx =75MHz

VC33-150

150

Supply current core CPU||k

TC =25°C,

fx =60MHz

VC33-120

IDDC

Supply current, core CPU||k

TC = 25 C,

CVDD =MAX

fx =75MHz

VC33-150

100

PLL enabled, oscillator enabled

IDD

IDLE2, Supply current, IDDD plus IDDC

PLL disabled, oscillator enabled

500

IDD

IDLE2, Supply current, IDDD plus IDDC

PLL disabled, oscillator disabled, FCLK = 0

100

μA

Input capacitance

All inputs except XIN

Input capacitance

XIN

Output capacitance

† All voltage values are with respect to VSS.

‡ For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

§ For VC33, all typical values are at DVDD =3.3,CVDD =1.8 V, TC (case temperature) = 25°C.

¶ Pins with internal pullup devices: TDI, TCK, and TMS. Pin with internal pulldown device: TRST.

# Pins D0--D31 include internal bus keepers that maintain valid logic levels when the bus is not driven (see Figure 9).

|| Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which

are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern at the

maximum rate possible. See TMS320C3x General-Purpose Applications User’s Guide (literature number SPRU194).

fx is the PLL output clock frequency.

PARAMETER MEASUREMENT INFORMATION

Tester Pin

Electronics

VLoad

IOL

IOH

Output

Under

Test

50 Ω

Where:

IOL

= 4 mA (all outputs) for DC levels test.

IO and IOH are adjusted during AC timing analysis to achieve an AC termination of 50 Ω

VLOAD =DVDD/2

= 40-pF typical load-circuit capacitance

Figure 15. Test Load Circuit

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