TLV9302IDDFR datasheet(7/61 Pages) TI2

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6.7 Electrical Characteristics

For VS = (V+) – (V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and

VOUT = VS / 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

VOS

Input offset voltage

VCM = V–

±0.5

±2.5

TA = –40°C to 125°C

±2.75

dVOS/dT

Input offset voltage drift

TA = –40°C to 125°C

±2

µV/

℃

PSRR

Input offset voltage versus

power supply

VCM = V–

TA = –40°C to 125°C

±2

±5

µV/V

Channel separation

f = 0 Hz

µV/V

INPUT BIAS CURRENT

Input bias current

±10

IOS

Input offset current

±10

NOISE

Input voltage noise

f = 0.1 Hz to 10 Hz

µVPP

µVRMS

Input voltage noise density

f = 1 kHz

nV/√Hz

f = 10 kHz

Input current noise

f = 1 kHz

fA/√Hz

INPUT VOLTAGE RANGE

VCM

Common-mode voltage

range

(V–) – 0.2

(V+) – 2

CMRR

Common-mode rejection

ratio

VS = 40 V, (V–) – 0.1 V < VCM

< (V+) – 2 V

TA = –40°C to 125°C

110

VS = 4.5 V, (V–) – 0.1 V <

VCM < (V+) – 2 V

(V+) – 2 V < VCM < (V+) + 0.1

See Common-Mode Voltage Range

INPUT CAPACITANCE

ZID

Differential

110 || 4

MΩ || pF

ZICM

Common-mode

6 || 1.5

TΩ || pF

OPEN-LOOP GAIN

AOL

Open-loop voltage gain

VS = 40 V, VCM = V–

(V–) + 0.1 V < VO < (V+) –

0.1 V

120

130

TA = –40°C to 125°C

116

127

FREQUENCY RESPONSE

GBW

Gain-bandwidth product

MHz

Slew rate

VS = 40 V, G = +1, CL = 20 pF

V/µs

Settling time

To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF

µs

To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF

2.5

To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF

To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF

3.5

Phase margin

G = +1, RL = 10 kΩ, CL = 20 pF

Overload recovery time

VIN × gain > VS

µs

THD+N

Total harmonic distortion +

noise

VS = 40 V, VO = 1 VRMS, G = -1, f = 1 kHz

0.003%

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TLV9301, TLV9302, TLV9304

SBOS941D – FEBRUARY 2019 – REVISED AUGUST 2021

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