SLAS616 datasheet(5/52 Pages) TI2

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MSP430FE42x2

MIXED SIGNAL MICROCONTROLLER

SLAS616 − JULY 2008

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

R13

Input port of third most positive analog LCD level (V4 or V3)

R23

Input port of second most positive analog LCD level (V2)

R33

Output port of most positive analog LCD level (V1)

P2.1/UCLK0/S24

I/O

General-purpose digital I/O / External clock input-USART0/UART or SPI mode, clock output—USART0/SPI

mode / LCD segment output 24 (See Note 1)

P2.0/TA2/S25

I/O

General-purpose digital I/O / Timer_A Capture: CCI2A input, Compare: Out2 output / LCD segment output

25 (See Note 1)

P1.7/SOMI0/S26

I/O

General-purpose digital I/O / Slave out/master in of USART0/SPI mode / LCD segment output 26

(See Note 1)

P1.6/SIMO0/S27

I/O

General-purpose digital I/O / Slave in/master out of USART0/SPI mode / LCD segment output 27

(See Note 1)

P1.5/TACLK/

ACLK/S28

I/O

General-purpose digital I/O / Timer_A and SD16 clock signal TACLK input / ACLK output

(divided by 1, 2, 4, or 8) / LCD segment output 28 (See Note 1)

P1.4/S29

I/O

General-purpose digital I/O / LCD segment output 29 (See Note 1)

P1.3/SVSOUT/

S30

I/O

General-purpose digital I/O / SVS: output of SVS comparator / LCD segment output 30 (See Note 1)

P1.2/TA1/S31

I/O

General-purpose digital I/O / Timer_A, Capture: CCI1A, CCI1B input, Compare: Out1 output / LCD segment

output 31 (See Note 1)

P1.1/TA0/MCLK

I/O

General-purpose digital I/O / Timer_A, Capture: CCI0B input / MCLK output.

Note: TA0 is only an input on this pin / BSL receive

P1.0/TA0

I/O

General-purpose digital I/O / Timer_A, Capture: CCI0A input, Compare: Out0 output / BSL transmit

TDO/TDI

I/O

Test data output port. TDO/TDI data output or programming data input terminal.

TDI/TCLK

Test data input or test clock input. The device protection fuse is connected to TDI.

TMS

Test mode select. TMS is used as an input port for device programming and test.

TCK

Test clock. TCK is the clock input port for device programming and test.

RST/NMI

Reset input or nonmaskable interrupt input port

P2.5/URXD0

I/O

General-purpose digital I/O / Receive data in—USART0/UART mode

P2.4/UTXD0

I/O

General-purpose digital I/O / Transmit data out—USART0/UART mode

P2.3/SVSIN

I/O

General-purpose digital I/O / Analog input to brownout, supply voltage supervisor

AVSS

Analog supply voltage, negative terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive

divider circuitry.

DVSS

Digital supply voltage, negative terminal.

AVCC

Analog supply voltage, positive terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive

divider circuitry; must not power up prior to DVCC.

NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.

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