MSP430FE42x2

MIXED SIGNAL MICROCONTROLLER

SLAS616 − JULY 2008

34

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

flash memory

PARAMETER

TEST

CONDITIONS

VCC

MIN

TYP

MAX

UNIT

VCC(PGM/

ERASE)

Program and erase supply voltage

2.7

3.6

V

fFTG

Flash timing generator frequency

257

476

kHz

IPGM

Supply current from DVCC during program

2.7 V/ 3.6 V

3

5

mA

IERASE

Supply current from DVCC during erase

2.7 V/ 3.6 V

3

7

mA

tCPT

Cumulative program time

See Note 1

2.7 V/ 3.6 V

10

ms

tCMErase

Cumulative mass erase time

See Note 2

2.7 V/ 3.6 V

200

ms

Program/erase endurance

104

105

cycles

tRetention

Data retention duration

TJ = 25°C

100

years

tWord

Word or byte program time

See Note 3

35

tFTG

tBlock, 0

Block program time for first byte or word

See Note 3

30

tFTG

tBlock, 1-63

Block program time for each additional byte or word

See Note 3

21

tFTG

tBlock, End

Block program end-sequence wait time

See Note 3

6

tFTG

tMass Erase

Mass erase time

See Note 3

5297

tFTG

tSeg Erase

Segment erase time

See Note 3

4819

tFTG

NOTES:

1. The cumulative programming time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all

programming methods: individual word/byte write and block write modes.

2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To

achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.

(A worst case minimum of 19 cycles are required).

3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).

JTAG interface

PARAMETER

TEST

CONDITIONS

VCC

MIN

TYP

MAX

UNIT

f

TCK input frequency

see Note 1

2.2 V

0

5

MHz

fTCK

TCK input frequency

see Note 1

3 V

0

10

MHz

RInternal

Internal pull-up resistance on TMS, TCK, TDI/TCLK

see Note 2

2.2 V/ 3 V

25

60

90

k

Ω

NOTES:

1. fTCK may be restricted to meet the timing requirements of the module selected.

2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.

JTAG fuse (see Note 1)

PARAMETER

TEST

CONDITIONS

VCC

MIN

MAX

UNIT

VCC(FB)

Supply voltage during fuse-blow condition

TA = 25°C

2.5

V

VFB

Voltage level on TDI/TCLK for fuse-blow

6

7

V

IFB

Supply current into TDI/TCLK during fuse-blow

100

mA

tFB

Time to blow fuse

1

ms

NOTES:

1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched

to bypass mode.