SLAS455D datasheet(9/67 Pages) TI2

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MSP430F42x0

MIXED SIGNAL MICROCONTROLLER

SLAS455D − MARCH 2005 − REVISED APRIL 2007

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh−0FFE0h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 3. Interrupt Sources, Flags, and Vectors of MSP430F42x0 Configuration

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD

ADDRESS

PRIORITY

Power-Up

External Reset

Watchdog

Flash Memory

PC Out-of-Range (see Note 4)

WDTIFG

KEYV

(see Note 1)

Reset

0FFFEh

15, highest

NMI

Oscillator Fault

Flash Memory Access Violation

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1 and 3)

(Non)maskable

0FFFCh

0FFFAh

SD16_A

SD16CCTLx SD16OVIFG,

SD16CCTLx SD16IFG

(see Notes 1 and 2)

Maskable

0FFF8h

0FFF6h

Watchdog Timer

WDTIFG

Maskable

0FFF4h

0FFF2h

0FFF0h

0FFEEh

Timer_A3

TACCR0 CCIFG0 (see Note 2)

Maskable

0FFECh

Timer_A3

TACCR1 CCIFG1 and TACCR2 CCIFG2,

TAIFG (see Notes 1 and 2)

Maskable

0FFEAh

I/O Port P1 (Eight Flags)

P1IFG.0 to P1IFG.7 (see Notes 1 and 2)

Maskable

0FFE8h

DAC12

DAC12_0IFG

(see Note 2)

Maskable

0FFE6h

0FFE4h

I/O Port P2 (Eight Flags)

P2IFG.0 to P2IFG.7 (see Notes 1 and 2)

Maskable

0FFE2h

Basic Timer1

BTIFG

Maskable

0FFE0h

0, lowest

NOTES:

1. Multiple source flags

2. Interrupt flags are located in the module.

3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot

disable it.

4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from

within unused address ranges (MSP430F4270, MSP430F4260: from 0300h to 0BFFh and from 01100h to 07FFFh,

MSP430F4250: from 0300h to 0BFFh and from 01100h to 0BFFFh).

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