LP55231 datasheet(43/59 Pages) TI2

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LP55231

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SNOSCR5D – MARCH 2013 – REVISED DECEMBER 2016

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7.6.6.2 INT

Send interrupt to processor by pulling the INT pin down and setting corresponding status bit high. Interrupt can

be cleared by reading interrupt bits in STATUS/INTERRUPT register at address 3A.

NAME

VALUE

DESCRIPTION

int

No interrupt is sent. PWM register valuesremain intact.

Reset program counter value to 0 and send interrupt to processor by pulling the INT pin down

and setting corresponding status bit high to notify that program has ended. PWM register

values remain intact. Interrupt can be cleared by reading interrupt bits in STATUS/INTERRUPT

reset

Reset program counter value to 0 and hold. PWM register values remain intact.

Reset program counter value to 0 and hold. PWM register values of the non-mapped drivers

remain.

PWM

values

the

mapped

drivers

are

set

0000

0000.

On completion of int instruction with this bit set to 1 the master fader registers are set to zero

as follows: Program execution engine 1 sets MASTER FADER 1 (48H) to zero, engine 2 sets

MASTER FADER 2 (49H) to zero and engine 3 sets MASTER FADER 3 (4AH) to zero.

7.6.6.3 RST

Rst instruction resets Program Counter register (address 37H, 38H, or 39H) and continues executing the

program from the program start address defined in 4C-4E. Instruction takes sixteen 32-kHz clock cycles. Note

that default value for all program memory registers is 0000H, which is the rst instruction.

7.6.6.4 END

End program execution. Instruction takes sixteen 32-kHz clock cycles.

7.6.6.5 TRIGGER

Wait or send triggers can be used to, for example, synchronize operation between the program execution

engines. Send trigger instruction takes sixteen 32-kHz clock cycles and wait for trigger takes at least sixteen 32-

kHz clock cycles. The receiving engine stores the triggers which have been sent. Received triggers are cleared

by wait for trigger instruction. Wait for trigger instruction is executed until all the defined triggers have been

received. (Note: several triggers can be defined in the same instruction.)

External trigger input signal must stay low for at least two 32-kHz clock cycles to be executed. Trigger output

signal is three 32-kHz clock cycles long. External trigger signal is active low, for example, when trigger is

sent/received the pin is pulled to GND. Send external trigger is masked; that is, the device which has sent the

trigger does not recognize it. If send and wait external trigger are used on the same instruction, the send external

trigger is executed first, then the wait external trigger.

NAME

VALUE (d)

DESCRIPTION

wait for trigger

0 - 31

Wait for trigger from the engine(s). Several triggers can be defined in the same instruction.

Bit [7] engages engine 1, bit [8] engine 2, bit [9] engine 3 and bit [12] is for external trigger

I/O. Bits [10] and [11] are not in use.

send a trigger

0 - 31

Send a trigger to the engine(s). Several triggers can be defined in the same instruction. Bit

[1] engages engine 1, bit [2] engine 2, bit [3] engine 3 and bit [6] is for external trigger I/O.

Bits [4] and [5] are not in use.

The LP55231 instruction set includes the following conditional jump instructions: jne (jump if not equal); jge (jump

if greater or equal); jl (jump if less); je (jump if equal). If the condition is true, a certain number of instructions are

skipped (that is, the program jumps forward to a location relative to the present location). If condition is false, the

next instruction is executed.

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