EF6805P2 datasheet(5/31 Pages) STMICROELECTRONICS

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Figure 2 : TTL Equivalent Test Load (port B).

Figure 3 : CMOS Equivalent Test Load (port A).

Figure 4 : TTL Equivalent Test Load (port A

andC).

Figure 5 : Open-drain Equivalent Test Load (port

C).

SIGNAL DESCRIPTION

The input and output signals for the MCU, shown in

figure 1, are described in the following paragraphs.

VCC AND VSS - Power is supplied to the MCU using

these two pins. VCC is power and VSS is the ground

connection.

INT - This pin provides the capability for asynchro-

nously applying an external interrupt to the MCU.

Refer to Interrupts Section for additional informa-

tion.

XTAL AND EXTAL - These pins provide control in-

put for theon-chip clock oscillator circuit. A crystal,

a resistor, or an external signal, depending on user

selectable manufacturing mask option, can be

connected to these pins to provide a system clock

with various degrees of stability/cost tradeoffs. Lead

length and stray capacitance on these two pins

should be minimized. Refer to Internal Clock Gen-

erator Options Section for recommendations about

these inputs.

NOTE : Pin 7 in DIL package/pin 8 in PLCC

package is connected to internal protection.

TIMER - The pin allows an external input to be used

to control the internal timer circuitry and also to ini-

tiate the self test program. Refer to Timer Section for

additional information about the timer circuitry.

RESET - This pin allows resetting of the MCU at

times other than the automatic resetting capability

already in the MCU. The MCU can be reset by pul-

ling RESET low. Refer to Resets Section for addi-

tional information.

EF6805U3

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EF6805P2 датащи(PDF) 5 Page - STMicroelectronics