VNF1048F datasheet(33/49 Pages) STMICROELECTRONICS

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Bit

Default

Name

Description

Access

The Low current bypass is rearmed via SPI. A transition to wake-up mode

causes this bit to be set to 1.

FUSE_LATCH

Current vs time latch-off: an overcurrent shutdown of the MOSFET

(FUSE_LATCH = 1) and the bypass switch occurs when the current sense

voltage exceeds the preset threshold for longer than the preset time (I2-t

curve emulating a traditional fuse).

The MOSFET and bypass switch are rearmed via SPI.

R/C

OVC

Overcurrent warning: an overcurrent warning (OVC = 1) occurs even when

average current sense value evaluated in a time interval equal to tI_SAMPLING

(time basis used by fuse emulation algorithm) exceeds current threshold

programmed through OVC_THR.

This is a “real-time” bit

OVC bit keeps memory of the previous events: once this bit is set, it will be

reset automatically after a time depending on current level previously reached

and on the related timings.

Moreover, after a FUSE_LATCH bit setting, OVC will be automatically reset in

a time interval proportional to the TNOM value previously programmed

(provided that in the meantime FUSE_LATCH is not cleared, high-side

restarts and current is again above OVC_THR).

Resetting FUSE_LATCH bit when OVC bit is still set to 1 is possible, but in

this case user can expect that trip time will be lower than expected.

DEV_OVT

Overtemperature shutdown (“real-time” bit). When DEV_OVT = 1, the

MOSFET, the charge pump and the bypass switch are turned off.

NTC_OVT

External MOS overtemperature: this bit is latched when NTC is lower than

NTC_THR. When NTC_OVT = 1 both external MOS and bypass switch are

turned off. The MOSFET and the bypass switch are rearmed via SPI.

R/C

VGS_LOW

This bit is set in on-state when VGS falls below UV threshold (VGS_UVLO_10V)

for more than VG_UVLO_DEGLITCH. When this bit is set, external FET is

switched off.

R/C

CP_LOW

This bit is set when VCP falls below VCP_LOW threshold for more than

tCP_RISE. When this bit is set, external FET driver is disabled. This is a “real-

time” bit.

WD_FAIL

Watchdog failure bit:

0: Watchdog OK;

1: Watchdog failure in unlocked / self-test states

When this bit is set, device goes to locked state. To go back to the unlocked

mode through the GoToUnlocked sequence this bit must be cleared.

R/C

Parity bit

Odd parity bit check

Table 39. SR#2: status register 2; address 12h

Bit

Default

Name

Description

Access

23 ÷ 15

Unused

14 ÷ 2 0000000000000 CURR_SENSE

13 bit ADC conversion related to current sense amplifier, ranging from 0

V to 160 mV; unidirectional current through an external sense resistor.

UPDT_CURR

Updated status bit. This bit is set when value is updated and cleared

when register is read.

Parity bit

Odd parity bit check

VNF1048F

SPI functional description

DS13084 - Rev 8

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