VNF1048F datasheet(17/49 Pages) STMICROELECTRONICS

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Figure 6. Current sense self-test flow sequence

Current sense

Self-test

Configuration

CR#1→ S_T_CFG = --1

CR#2→ OVC_THR = <user option>

CR#2 →HSHT_THR = <user option>

SELF-TEST CONFIGURATION

Turn-on pull-down current generator to produce

additional voltage drop of 100 mV on current sense

amplifier inputs

A/D CONVERSIONS AND DELTA MEASURES

Perform current sense SAR A/D conversions

Compute difference between self-test measures and

last user measure available in status register SR#8

Store data result, self-test status and fault emulation

check in status register SR#7

UNLOCKED STATE

SELF-TEST STATE

Current sense

Self-test

Execution

Current sense

Self-test

END

UNLOCKED STATE

S_T_START = 1

LOCKED

S_T_STOP = 1

WD Timeout

HWLO = 1

TS_T_ACTIVE time duration

CURRENT SENSE SELF-TEST

SELF-TEST CLOSURE

Turn-off pull-down current generator to restore

normal drop on current sense amplifier inputs

No current sense A/D conversions during this

timeframe

TS_T_WAITtime duration

During TS_T_ACTIVE and TS_T_WAIT

timeframes, fast and slow

trip protections are

inhibited, whilst all other

protections are active

00 = IDLE

01 = RUN

10 = END

11 = ABORT

Parity

Status

ADC Self Test Result

OVC_ST

HSHT_ST

(Selftest aborted, state

transition after TS_T_WAIT

expiration)

(Selftest aborted,

state transition

after TS_T_WAIT

expiration)

TEST COMPLETED

TS_T_ACTIVE = 5 μs

TS_T_WAIT = 5 μs

Current sense

Self-test

Configuration

4.2

External FET VDS detection self-test

The purpose of the external FET VDS detection self-test is to verify the proper behavior of the complete VDS

monitor chain (sense/process/detection), from the analog input to the digital output.

Starting from the unlocked state, the VDS detection self-test is activated through a dedicated SPI frame. The

duration of this test is around 10 μs; the first 5 μs are intended to convert the value of the voltage across the drain

and source terminals of the external FET, the remaining 5 µs are required to bring back the analog circuitry to

normal configuration.

Once the self-test is started, an internal current generator provides a current sink able to produce an additional

voltage offset of 100 mV on VDS monitor circuit inputs, to distinguish self-test execution from normal operation. In

order to guarantee proper data conversions, special care must be taken to avoid VDS ADC saturation by keeping

the overall VDS sensed by the monitor circuit below the maximum scale range (VDS_ADC_CONV).

VDS detection self-test result is the difference between the converted value obtained during self-test execution

and the value already stored in SR#4 (VDS field), corresponding to the normal measurement performed during

operation; such delta measure result is stored in SR#5 (S_T_VDS field) together with the self-test status.

VNF1048F

Self-test

DS13084 - Rev 8

page 17/49

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