VNF1048F datasheet(19/49 Pages) STMICROELECTRONICS

19 / 49 page

Starting from the unlocked State, the external FET stuck-on self-test is activated through a dedicated SPI frame

(CR#1, S_T_START & S_T_CFG fields).

At execution start the external FET is automatically turned-off, regardless of its status during previous operations,

then continuous AtoD conversions of VDS voltage, sensed across external power switch terminals, are performed

in order to allow the user to monitor VDS evolution in time.

Data conversion values are made available through dedicated register SR#6 (S_T_STUCK field); in addition, a

specific bit informs the user if the data have been updated with a new measure or are still relative to the previous

one (UPDT_S_T_STUCK bit). Status of self-test execution is available in the same register.

Self-test completion can be controlled directly by sending the S_T_STOP command (CR#1, bit 8) or by setting the

programmable VDS threshold (CR#2, VDS_THR field): in this case, self-test is stopped automatically as soon as

the external FET VDS overcomes the previously mentioned threshold and a specific bit is set to flag this situation

(SR#6, S_T_VDS_MAX2 bit). In both cases, device FSM performs the transition from self-test to unlocked state.

To be noted that the diagnostic fault for normal operation (VDS_MAX, SR#1) is inhibited during execution, while

all the others are kept enabled; bypass switch control is left to the user.

The transition from the self-test state to the locked state can occur in case of watchdog timeout or HWLO = 1

(self-test aborted).

Figure 8. External FET stuck-on self-test - flow sequence for entry

External FET

Stuck-on self-test

Configuration

External FET

Stuck-on

Self-test

Configuration

SELF-TEST CONFIGURATION

Turn OFF the External FET

CONTINUOUS A/D CONVERSIONS

Perform continuous A/D conversion of VDS

Store the result in Status Register SR#6

UNLOCKED STATE

External FET = ‘OUTCTL’

BYPASS = ‘BYPASSCTL”

SELF-TEST STATE

External FET is OFF

BYPASS = ‘BYPASSCTL’

External FET

Stuck-on self-test

Execution

External FET

Stuck-on self-test

END

UNLOCKED STATE

External FET = ‘OUTCTL’

BYPASS = ‘BYPASSCTL”

S_T_START = 1

LOCKED

S_T_STOP = 1

WD Timeout

HWLO = 1

During Selftest

execution, VDS

protection is inhibited

EXTERNAL FET STUCK-ON SELF-TEST

VDS > VDS_THR

TEST COMPLETED

00 = IDLE

01 = RUN

10 = END

11 = ABORT

Parity

Status

ADC Self Test Result

S_T_VDS_MAX2

UPDT_S_T_STUCK

CR#1→ S_T_CFG = 1--

CR#2→ VDS_THR = <user option>

(Selftest aborted)

(Selftest completed)

VNF1048F

Self-test

DS13084 - Rev 8

page 19/49

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